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Improving Linearity of Limiter and LNA for Blocker Tolerant RF Receivers

Jarollahi, Bahar | 2025

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  1. Type of Document: Ph.D. Dissertation
  2. Language: Farsi
  3. Document No: 58732 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Medi, Ali; Meghdadi, Masoud
  7. Abstract:
  8. Low-noise amplifiers (LNAs) are widely used in various types of receivers and are considered one of their key components. In certain applications, particularly those involving amplitude modulation, it is essential for LNAs to exhibit not only low noise performance but also high linearity, ensuring that as the input power increases, the amplifier can handle higher levels without saturation or signal distortion. Additionally, due to the proximity of transmitters and receivers and the potential presence of high-power blockers at the receiver input, it is often necessary to employ a power limiter at the input of the LNA to prevent excessive power from damaging the amplifier. Since the insertion loss of the limiter directly affects the receiver’s noise figure, the power limiter must not only provide effective protection but also introduce minimal loss to maintain optimal noise performance. In this study, a low-loss, transistor-based reflective structure for power limiting is introduced. Given the critical importance of minimizing leakage power, a method for reducing leakage without increasing insertion loss is also proposed and analyzed. Due to its low insertion loss, the proposed power limiter is well-suited for low-noise receiver applications. Moreover, owing to its reflective configuration, approximately 70% of the input power is reflected back at high input power levels, significantly reducing on-chip power dissipation and thereby preventing excessive temperature rise. The power limiter is implemented using a 0.15 μm AlGaAs-InGaAs pseudomorphic HEMT (pHEMT) process, occupies an area of 0.8 mm², and is capable of handling up to 5 W of continuous wave (CW) power over the 4–6 GHz frequency band. It achieves a minimum insertion loss of 0.83 dB with a variation of 0.17 dB across the specified frequency range. Owing to the chosen technology, the limiter can be monolithically integrated with a low-noise amplifier, which enables the integration of matching networks, leading to improved overall noise figure and reduced system-level costs, including assembly expenses. In the next part of this study, the codesign and integration of a limiter and an LNA on a single technology platform are presented. In addition to the previously introduced leakage reduction method, a new technique is proposed that significantly reduces output leakage power without increasing the limiter’s insertion loss. The integrated limiter–LNA employs a novel biasing circuit that exhibits substantially lower sensitivity to process and temperature variations (approximately ±12%) compared to conventional methods used for biasing pHEMTs in depletion mode. Furthermore, a gain control technique is introduced that does not degrade the overall noise figure or linearity of the system. As a result, an integrated limiter–LNA chip has been designed and fabricated in 0.15 μm AlGaAs-InGaAs pHEMT technology, capable of handling 10 W CW power in the 8.5–10.5 GHz frequency band, offering a gain of 25 dB, gain reduction capability of 8 dB, an average noise figure of 2.1 dB, and an output 1-dB compression point of 14 dBm. In addition to this chip, the architectures and measurement results of two other integrated limiter–LNA chips are presented: one operating in the C-band, employing an innovative linearity enhancement method, and the other in the Ka-band, featuring a novel approach for integrating the limiter with an SPDT switch and an attenuator.
  9. Keywords:
  10. Low Noise Amplifier (LNA) ; Pseudo High Electron Mobility Field Effect Transistor (pHEMT) ; Noise Figure ; Receiver with Power Limiter ; Linearity Improvement ; High Power Tolerable

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