Sharif Digital Repository

This paper presents a method for optimizing SFDR in differential active-RC filters. Simple analytical expressions for noise and third-order intermodulation (IM3) distortion in active-RC filters are derived. The nonlinear behavior of two-stage Miller-compensated op amps, which are extensively used in active-RC implementations, is also modeled. These expressions and models are used to maximize SFDR in active-RC filters by means of proper admittance scaling and optimizing the share of each op amp in the total power consumption. It is shown that both the power consumption of the filter and its area can be significantly reduced, for a given SFDR, by exploiting the presented method  

This paper presents a design procedure for a wideband 6-18-GHz monolithic microwave integrated circuit highpower amplifier (HPA) in 0.25-μm AlGaAs-InGaAs pHEMT technology. The design is mainly focused on the realization of the passive circuits to provide the required low-loss and wideband impedance transformation networks. The two-stage GaAs HPA achieves an average output power of 39.6 dBm and a peak output power of 40.5 dBm at 11 GHz, in pulsed mode operation, with a small-signal gain of S21 > 10 dB over the entire bandwidth. The average power added efficiency (PAE) is 22%, with a peak PAE of 29% at 11 GHz. The HPA chip occupies an area of 5×3.6 mm2. The achieved output power and the... 

This paper presents a general method for real-time adaptation of wireless receivers according to the prevailing reception conditions. In order to maintain the desired signal quality at the minimum possible power dissipation, the method performs an optimal trade-off between noise, linearity, and power consumption in the building blocks of the receiver. This is achieved by continuously monitoring the signal-to-noise plus interference ratio (SNIR) and accordingly tuning the adaptation parameters embedded in the receiver design. A prototype DVB-H receiver chip, implemented in a standard 0.18-μ m CMOS process, is used as the test vehicle. By properly trading noise with linearity in the receiver,... 

A new approach for the design of two-stage Miller-compensated CMOS op amps is presented. The paper studies the basic relations between power consumption, unitygain bandwidth, the biasing region, technology parameters, and the external capacitive load. As a result, simple and efficient design guides are provided to achieve the minimum possible power consumption for the given specifications and for short-channel devices. It is shown that the conventional design procedures do not always result in minimum power op amps. The presented results are also verified by Spectre simulations  

A highly linear X-band low-noise amplifier (LNA) is proposed and implemented in a standard 0.18-μm CMOS technology. The LNA features both high and low-gain operation modes. In its normal high-gain mode, the LNA shows a small-signal gain of 13.6 dB with an IIP3 of +9.5 dBm and a noise figure of 4.7 dB. The two-stage amplifier draws 90 mA from the 3.3V power supply to achieve +14.8 dBm output P1dB (+2.2 dBm input P1dB). In the low-gain mode, the gain is reduced by about 10 dB to further enhance the linearity and to accommodate very large blockers. Accordingly, the input P1dB is enhanced to +13.7 dBm while the noise figure is increased by 8.1 dB. A technique is also introduced to maintain the... 

This paper presents a highly-linear transceiver core chip for X-band phased-array systems with two RX and one TX channels. Implemented in a standard 0.18-μm CMOS technology, the core chip provides 6-bit phase control (with rms error <2°) and 6-bit gain control (with rms error <0.6 dB) both within the 8.5–11.5 GHz frequency band. Improved accuracy is also available by digital calibration in narrowband applications. The receivers achieve a gain of 13.5 dB, an IIP3 of +10.3 dBm, and a noise figure of 8.2 dB, while drawing 170 mA per channel from the 3.3 V supply. The chip also provides an additional low-gain mode which further enhances IIP3 to +19.1 dBm and the input-referred P1dB to +11.4 dBm.... 

This article presents the theory and implementation of a quadrature and differential RF front-end receiver. Combining balun, low-noise amplifier (LNA), mixer, and oscillator in a single stage, the proposed circuit, named the Blixator, is well suited for low-power applications. The baseband's transimpedance amplifier (TIA) also shares part of its dc current with the Blixator cell, resulting in sub-milliwatt power consumption. To avoid additional power and area by quadrature LO generation, the I/Q signals are generated at RF, employing the inductors already required for providing the dc current path of the LNA transistors. The expressions for gain, noise figure (NF), and phase noise of the... 

This paper introduces a reflective, low insertion loss transistor-based limiter based on a new leakage reduction method. The effectiveness of the proposed limiter has been confirmed through simulation and measurement results. Due to its low insertion loss, the proposed limiter is suitable for low-noise receivers. It reflects approximately 70% of the input power, leading to lower temperature rise, when subjected to high incident power, compared to absorptive limiters. Fabricated using a low-noise 0.15-μm AlGaAs–InGaAs pseudomorphic HEMT (pHEMT) technology, this design allows for co-design with a low noise amplifier (LNA) on the same die. Measurement results have demonstrated that the proposed... 

Urban area regeneration is a matter of every municipality over time. Regeneration projects are usually cost-intensive and directly affect many vulnerable members of society. Public-private-people partnership (PPPP) is one of the adopted methods by various municipalities in these projects. Multiple players with different backgrounds and uncertainties involved complicate the development process of PPPP projects. A carefully designed framework is required to successfully deliver these projects. This research develops a holistic PPPP framework for the old urban neighborhood regeneration projects in Iran. The collective experience of urban area regeneration projects from the literature and field... 

A wide-input/output-voltage-range buck converter with adaptive light-load efficiency improvement and seamless mode transition for high-voltage applications is presented in this article. The proposed design uses a load prediction structure to eliminate dc current sensor and to ensure high efficiency in the 0.02∼2-A load range. The pulsewidth modulation (PWM) mode has been used for near-full load. Since efficiency degradation at light loads occurs at different levels regarding the input and output voltage, a novel dynamic frequency pulsewidth modulation (DFPWM) with adaptive efficiency improvement mechanism is proposed, which activates efficiency improvement based on the input and output... 

A 6-bit passive phase shifter for 2.5- to 3.2-GHz frequency band has been designed and implemented in a standard 0.18- μm CMOS technology. A new switched-network topology has been proposed for implementing the 5.625 ° phase shift step. The insertion loss of the circuit is compensated with an on-chip bidirectional amplifier. The measured return losses of the circuit are better than 8 dB with output 1-dB compression point of +9.5 dBm in the transmit mode and noise figure of 7.1 dB in the receive mode. The fabricated phase shifter demonstrates an average rms phase error of less than 2° over the entire operation bandwidth, which makes it suitable for high-precision applications  

In this article, a design methodology is presented to realize integrated class-F high-power amplifiers (HPAs). A harmonic-control network (HCN) is proposed to present short- and open-circuit impedances to each transistor employed in the output stage of the HPA at 2f_0 and 3f_0 frequencies. The HCN absorbs the parasitic capacitance of the transistor and lends itself to be absorbed in the matching and power combiner networks, reducing the die area of the HPA. A proof-of-concept 9.7-10.3-GHz class-F HPA was designed and implemented in a 0.25-μm GaAs pHEMT technology with VDD of 6 V. The designed HPA consists of two amplifying stages, and its output stage includes 16 transistors in parallel to... 

In this article, a design methodology is presented to realize integrated class-F high-power amplifiers (HPAs). A harmonic-control network (HCN) is proposed to present short- and open-circuit impedances to each transistor employed in the output stage of the HPA at {2}f {0} and {3}f {0} frequencies. The HCN absorbs the parasitic capacitance of the transistor and lends itself to be absorbed in the matching and power combiner networks, reducing the die area of the HPA. A proof-of-concept 9.7-10.3-GHz class-F HPA was designed and implemented in a 0.25- μ ext{m} GaAs pHEMT technology with V {DD} of 6 V. The designed HPA consists of two amplifying stages, and its output stage includes 16... 

In this article, a design methodology is presented to realize integrated class-F high-power amplifiers (HPAs). A harmonic-control network (HCN) is proposed to present short- and open-circuit impedances to each transistor employed in the output stage of the HPA at {2}f {0} and {3}f {0} frequencies. The HCN absorbs the parasitic capacitance of the transistor and lends itself to be absorbed in the matching and power combiner networks, reducing the die area of the HPA. A proof-of-concept 9.7-10.3-GHz class-F HPA was designed and implemented in a 0.25- μ ext{m} GaAs pHEMT technology with V {DD} of 6 V. The designed HPA consists of two amplifying stages, and its output stage includes 16...