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  1. PartialHD: Toward efficient hyperdimensional computing by partial processing

PartialHD: Toward efficient hyperdimensional computing by partial processing

Taheri, F ; Sharif University of Technology | 2024

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  1. Type of Document: Article
  2. DOI: 10.1109/JIOT.2023.3287316
  3. Publisher: 2024
  4. Abstract:
  5. Hyperdimensional (HD) computing is a brain-inspired learning method that is widely employed in resource-constrained applications, such as the Internet of Things (IoT) regarding its lightweight computation. Although HD computing has high efficiency in the IoT applications, it suffers from high computation due to the large vector size. Thus, several studies are proposed to speedup and increase the efficiency of HD computing. In this work, we propose a method to process HD computing called PartialHD. Our method divides a long hypervector into multiple partial vectors and processes each vector separately. In the retraining phase, this method improves accuracy up to 1.93%. Moreover, by employing our proposed method in the retraining and inference, only a few partial vectors participate and this causes the computational overhead reduces in these phases. The evaluation shows that our method processes on average 22.2% and 36.23% of the entire hypervectors with negligible accuracy loss in inference and retraining, respectively. Furthermore, we propose two general architectures (lightweight and high-speed), which accelerate partial vector computations on different FPGA platforms. The result shows that the lightweight architecture can accelerate HD computing on resource-constrained FPGAs such as Artix while the high-speed architecture has 4.72× higher throughput than the lightweight architecture. © 2014 IEEE
  6. Keywords:
  7. Hyperdimensional (HD) computing ; Acceleration ; Efficiency ; Field programmable gate arrays (FPGA) ; Integrated circuit design ; Internet of things ; Job analysis ; Learning systems ; Signal encoding ; Vectors ; Encodings ; Field programmable gate array ; Field programmables ; FPGA design ; Hyperdimensional computing ; Light weight ; Programmable gate array ; Retraining ; Task analysis ; Training data ; Computer architecture
  8. Source: IEEE Internet of Things Journal ; Volume 11, Issue 1 , 2024 , Pages 987-994 ; 23274662 (ISSN)
  9. URL: https://ieeexplore.ieee.org/document/10155461