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| # | Type | Title | Author | Publisher | Pub. Year | Subjects | Call Number |
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| 1 | مقاله | ESL design of object-oriented applications: The ODYSSEY approach | Goudarzi, M. | Nova Science Publishers, Inc, | 2012 |
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| 2 | مقاله | The ODYSSEY tool-set for system-level synthesis of object-oriented models | Goudarzi, M. | Springer Verlag, | 2005 |
Automation.
Computer architecture. Embedded systems. Mathematical models. Natural language processing systems. ASIP hardware. Automatic synthesis. Error-prone language transformations. Polymorphism. Object oriented programming. |
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| 3 | مقاله | Infrastructure aware heterogeneous-workloads scheduling for data center energy cost minimization | Haghshenas, K. | Institute of Electrical and Electronics Engineers Inc, | 2022 |
Energy cost.
Free cooling. Internet data center (IDC) Renewable energy. Uninterruptible power supply. Computer aided software engineering. Cooling. Cost reduction. Energy utilization. Green computing. Meteorology. Scheduling. Solar energy. Solar power generation. Clean energy sources. Electricity rate structure. Heterogeneous workloads. High energy consumption. Internet data centers. Renewable energies. Synthetic workloads. Total energy consumption. Data reduction. |
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| 4 | مقاله | An efficient synchronization circuit in multi-rate SDH networks | Zare, M. | 2014 |
Multi-rate.
SYNC clock. Synchronization. Synchronous digital hierarchy. |
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| 5 | مقاله | Throughput enhancement for repetitive internal cores in latency-insensitive systems | Zare, M. | IEEE, | 2012 |
Actual system.
Area reduction. Latency-insensitive designs. Latency-insensitive Systems. Multiple iterations. Repetitive structure. Simulated system. Synchronous system. System on chip design. System throughput. Throughput enhancement. Throughput improvement. Digital communication systems. Software engineering. Throughput. |
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| 6 | مقاله | Efficient periodic clock calculus in latency-insensitive design | Zare, M. | 2011 |
Area overhead.
Area usage. Clock calculus. Clock gating. Communication wire. Critical issues. Interconnection. Latency-Insensitive. Latency-insensitive designs. Reduction in area. Scheduling schemes. System on chip design. Test case. Wire delays. Algorithms. Delay circuits. Microprocessor chips. Programmable logic controllers. Shift registers. Wire. Design. |
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| 7 | مقاله | Heuristic algorithm for periodic clock optimisation in scheduling-based latency-insensitive design | Zare, M. | Institution of Engineering and Technology, | 2015 |
Algorithms.
Application specific integrated circuits. Clocks. Design. Heuristic algorithms. Heuristic methods. Integrated circuit design. Microprocessor chips. Shift registers. System-on-chip. Wire. Bit sequences. Communication wire. Design iteration. Latency-insensitive designs. Optimisations. Real systems. Synthetic analysis. Synthetic benchmark. Scheduling. |
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| 8 | مقاله | Evaluation of distributed stream processing frameworks for IoT applications in smart cities | Nasiri, H. | SpringerOpen, | 2019 |
Distributed stream processing.
IoT applications. Latency. Smart City. Throughput. |
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| 9 | مقاله | Using on-chip networks to implement polymorphism in the co-design of object-oriented embedded systems | Goudarzi, M. | 2007 |
Chip scale packages.
Interconnection networks. Network routing. Polymorphism. Virtual reality. Application specific instruction processor (ASIP) Hardware software co-design. Network on chip (NoC) Object oriented design. Virtual method dispatch. Embedded systems. |
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| 10 | مقاله | A reconfigurable cache architecture for object-oriented embedded systems | Modarressi, M. | Institute of Electrical and Electronics Engineers Inc, | 2006 |
Buffer storage.
Embedded systems. Object oriented programming. Program processors. Application-specific instruction set processors (ASIP) Object-oriented embedded systems. Reconfigurable cache architecture. Computer architecture. |
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| 11 | مقاله | Software implementation of MPEG2 decoder on an ASIP JPEG processor | Mohammadzadeh, N. | 2005 |
Algorithms.
Computer hardware. Computer software. Decoding. Decompression algorithms. IDCT. MPEG2 decoder. ODYSSEY. Software implementation. Program processors. |
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| 12 | مقاله | Object-oriented embedded system development based on synthesis and reuse of OO-ASIPs | Goudarzi, M. | 2004 |
Application-specific instruction processors.
Embedded system design. Hardware/software synthesis. High-level synthesis. Object-oriented system design. |
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| 13 | مقاله | Object-aware cache: Higher hit-ratio in object-oriented ASIPs | Goudarzi, M. | 2004 |
Directed fetching policy.
Embedded system. Hardware data prefetch. Object-oriented ASIP. |
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| 14 | مقاله | Overhead-free polymorphism in network-on-chip implementation of object-oriented models | Goudarzi, M. | 2004 |
Computer hardware.
VLSI circuits. Exhibitions. Software prototyping. Packet switching. Microprocessor chips. Data communication systems. Computer simulation. Computer software. |
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| 15 | مقاله | Dynamically adaptive register file architecture for energy reduction in embedded processors | Khavari Tavana, M. | Elsevier, | 2015 |
Computer architecture.
Energy efficiency. Energy utilization. Application behaviors. Benchmark suites. Embedded processors. Energy reduction. Low Power. Processor architectures. Register files. Unused registers. Embedded systems. |
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| 16 | مقاله | A novel key partitioning schema for efficient execution of MapReduce applications | Nasehi Basharzad, S. | Institute of Electrical and Electronics Engineers Inc, | 2018 |
MapReduce.
Computer architecture. Data handling. Multiprocessing systems. Network architecture. Open source software. Computational problem. Hadoop. Large-scale distributed system. Map-reduce. Open source implementation. Partitioner. Performance. Programming models. Big data. |
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| 17 | مقاله | The ODYSSEY approach to early simulation-based equivalence checking at ESL level using automatically generated executable transaction-level model | Goudarzi, M. | 2008 |
Benchmarking.
Channel capacity. Chlorine compounds. Complexation. Computer programming languages. Large scale systems. Machine design. Model checking. Process engineering. System theory. Systems analysis. Telecommunication networks. Time measurement. Unified Modeling Language. Automatically generated. Before and after. Co-simulation. Complex designs. Design cycles. Design technologies. Electronic system-level. Equivalence checking. ESL design. Functional equivalence. Functional verifications. Hardware and software components. Hardware-software co-design. Hardware-software co-simulation. Level 2. Level model. Level of abstraction. New techniques. ODYSSEY methodology. Orders-of-magnitude. Simulation performance. Simulation speed. Simulation-based. Simulation-based verification. Synthesis process. Synthesis tools. SystemC. Transaction-level model. Verification strategy. Computer simulation. |
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| 18 | مقاله | Implementation of a jpeg object-oriented ASIP: A case study on a system-level design methodology | Mohammadzadeh, N. | 2007 |
Algorithms.
Automatic programming. Computer aided software engineering. Data structures. Decoding. Embedded systems. Program processors. Decoding algorithms. JPEG decoders. Logic blocks. System-level designs. Object oriented programming. |
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| 19 | مقاله | A framework for object-oriented embedded sysem development based on OO-ASIPS | Mohammadzadeh, N. | 2008 |
Application specific integrated circuits.
Computer aided design. Embedded software. Integrated circuits. Object oriented programming. Polymorphism. Systems analysis. Abstraction levels. Application-Specific Instruction Processor (ASIP) Design automation tool. Hardware and software components. Implementation process. Object-oriented design. Object-oriented modeling. Object-oriented specifications. Performance penalties. Real-world. Smooth transitions. Toolset. Top downs. Embedded systems. |
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| 20 | مقاله | A scheduling algorithm to maximize storm throughput in heterogeneous cluster | Nasiri, H. | Springer Science and Business Media Deutschland GmbH, | 2023 |
Heterogeneous.
Parallelism. Scheduling. Stream processing. Throughput. |
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