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| # | Type | Title | Author | Publisher | Pub. Year | Subjects | Call Number |
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| 1 | مقاله | An efficient STT-Ram last level cache architecture for GPUs | Samavatian, M. H. | 2014 |
GPGPU Application.
GPU. Retention Time. STT-RAM. Cache memory. Computer aided design. Program processors. Data retention time. Last-level caches. Low-power characteristics. Processing core. Write operations. Random access storage. |
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| 2 | مقاله | A game theoretical thermal - aware run-time task synchronization method for multiprocessor systems-on-chip | Asgarieh, Y. | 2012 |
Multiprocessor systems-on-chip.
Thermal aware design. Multi-core processor. Multiprocessor systems on chips. Optimal points. Peak temperatures. Performance. Runtimes. Task synchronization. Theory concept. Thermal constraints. Thermal-aware design. Game theory. Optimization. Systems analysis. Iterative methods. |
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| 3 | مقاله | ASHA: An adaptive shared-memory sharing architecture for multi-programmed GPUs | Abbasitabar, H. | Elsevier B.V, | 2016 |
Computer graphics.
Program processors. Execution scenario. GPGPU. Graphics processing units. Performance degradation. Resource requirements. Resource sharing. Shared memory. Thread-level parallelism. Memory architecture. |
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| 4 | مقاله | A compression-based morphable PCM architecture for improving resistance drift tolerance | Jalili, M. | 2014 |
Computer architecture.
Emerging technologies. Full system simulators. Memory system architectures. Memory systems. Multilevel cell. Phase change memory (PCM) Resistance drifts. Storage capability. Dynamic random access storage. |
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| 5 | مقاله | Reconfigurable cluster-based networks-on-chip for application-specific MPSoCs | Modarressi, M. | 2012 |
Cluster-based.
Communicating tasks. Communication infrastructure. Design flows. Evaluation results. Mesh topologies. Networks on chips. Reconfigurable. Short-path. Traffic management. Topology. Computer architecture. |
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| 6 | مقاله | On pancyclicity properties of OTIS networks | Hoseinyfarahabady, M. R. | Springer Verlag, | 2007 |
Algorithms.
Computational methods. Embedded systems. Graph theory. Hamiltonians. Problem solving. Algorithmic efficiency. Hamiltonian properties. OTIS networks. Computer networks. |
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| 7 | مقاله | The grid-pyramid: A generalized pyramid network | Hoseinyfarahabady, M. R. | 2006 |
Computer software.
Data structures. Embedded systems. Hamiltonians. Interconnection networks. Topology. Hamiltonian cycles. Hamiltonian path. Hamiltonian-connectivity. Hypermesh. Link-disjoint Hamiltonian cycles. Mesh. Pancyclicity. Pyramid. Torus. WK-recursive mesh. Distributed computer systems. |
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| 8 | مقاله | The Recursive Transpose-Connected Cycles (RTCC) interconnection network for multiprocessors | Farahabady, M. H. | 2005 |
Algorithms.
Computer networks. Graph theory. Hamiltonians. Hamiltonian properties. Implementation constraints. Multicomputer. Performance evaluation. Interconnection networks. |
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| 9 | مقاله | Sequoia: A high-endurance NVM-Based cache architecture | Jokar, M. R. | Institute of Electrical and Electronics Engineers Inc, | 2016 |
Lifetime.
Nonvolatile cache (NV-cache) Wear-leveling. Write endurance. Interference suppression. Leveling (machinery) Random access storage. Cache architecture. Cache configurations. Emerging Non-volatile memory technology. Lastlevel caches (LLC) Minimum interference. Novel techniques. Power efficient. Spin transfer torque. Cache memory. |
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| 10 | مقاله | Efficient SIMD numerical interpolation | Ahmadi, H. | Springer Verlag, | 2005 |
Algorithms.
Numerical analysis. Personal computers. Vectors. Interpolation algorithms. Pentium processors. SIMD. Vector algorithms. Interpolation. |
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| 11 | مقاله | Neda: supporting direct inter-core neighbor data exchange in GPUs | Nematollahi, N. | Institute of Electrical and Electronics Engineers Inc, | 2018 |
GPUs.
Inter-core communication. Neighbor data exchange. Spatial image processing filters. Computer graphics. Computer hardware. Electronic data interchange. Energy efficiency. Energy utilization. Graphics processing unit. Hardware-software codesign. Image enhancement. Image processing. Program processors. Instruction set. Inter-core communications. Microsoft windows. Registers. Spatial images. Two-dimensional displays. Computer architecture. |
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| 12 | مقاله | Design for scalability in enterprise SSDs | Tavakkol, A. | 2014 |
I/O interface.
Interconnection network. Solid state drive. Design. Integrated circuit interconnects. Interconnection networks (circuit switching) Interface states. Network architecture. Parallel architectures. Scalability. Communication paradigm. Conventional design. Design constraints. Flash memory chip. NAND flash memory. Performance and scalabilities. Scalability problems. |
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| 13 | مقاله | Prolonging lifetime of PCM-based main memories through on-demand page pairing | Asadinia, M. | 2015 |
Multilevel cell.
Page pairing. Cells. Cytology. Dynamic random access storage. Flash memory. Multiprogramming. Semiconductor storage. Correction schemes. Nano-meter regimes. Phase change memory (PCM) Process Variation. Semiconductor memory. Wear-leveling algorithms. |
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| 14 | مقاله | Reducing access latency of MLC PCMs through line striping | Hoseinzadeh, M. | 2014 |
Cytology.
Memory architecture. Access latency. Fundamental properties. Least significant bits. Memory access latency. Memory energies. Read latencies. Read operation. Storage capability. Cells. |
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| 15 | مقاله | Unleashing the potentials of dynamism for page allocation strategies in SSDs | Tavakkol, A. | 2014 |
Dynamism.
Page allocation. Parallel architectures. Internal resources. Its efficiencies. Solid state drives. Speed up. Static pages. Computer systems. |
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| 16 | مقاله | Using task migration to improve non-contiguous processor allocation in NoC-based CMPs | Modarressi, M. | 2013 |
Non-contiguous allocation.
Task migration. Network on chip. Non-contiguous allocation. Performance. Power. Processor allocation. Communication. Heuristic algorithms. Multiprocessing systems. Routers. VLSI circuits. Microprocessor chips. |
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| 17 | مقاله | OD3P: On-demand page paired PCM | Asadinia, M. | 2014 |
Lifetime.
Computer aided design. Error correction. Capacity degradation. Correction schemes. Error-correction schemes. Nano-meter regimes. Page pairing. Phase change memory (PCM) Write endurances. Dynamic random access storage. |
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| 18 | مقاله | Network-on-SSD: A scalable and high-performance communication design paradigm for SSDs | Tavakkol, A. | 2013 |
Interconnections (Subsystems)
Mass storage. Algorithmic techniques. Communication design. Communication schemes. Garbage collection. Solid state disks. Storage infrastructure. Communication. Flash memory. Microprocessor chips. Throughput. Data storage equipment. |
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| 19 | مقاله | Multicast-aware mapping algorithm for on-chip networks | Habibi, A. | 2011 |
Mapping.
End to end delay. Energy consumption. Energy saving. Heuristic approach. In-chip. IP core. Mapping algorithms. Mapping strategy. Multi core. Multicast. Multicast communication. Network-on-Chip. On chip communication. On-chip networks. Performance improvements. Real applications. Simulation result. Unicast flows. Unicast traffic. Algorithms. Conformal mapping. Energy utilization. Heuristic methods. Microprocessor chips. Servers. Telecommunication systems. VLSI circuits. Multicasting. |
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| 20 | مقاله | Supporting non-contiguous processor allocation in mesh-based chip multiprocessors using virtual point-to-point links | Asadinia, M. | 2012 |
Allocation algorithm.
Best fit. Chip multiprocessor. Communicating tasks. Communication infrastructure. Disjoint regions. Network on chip. On chip communication. Point-to-point link. Processing nodes. Processor allocation. Router pipeline. Runtimes. Algorithms. Microprocessor chips. Routers. Systems analysis. VLSI circuits. Pipeline processing systems. Arrival order. Contiguous techniques. Execution lifetime. Fit allocation algorithms. Greedy-available-busy-list algorithm. Interregion routers. Virtual point-to-point links. Stack-based allocation algorithms. Run-time incremental mapping. Run-time assignment. Latency reduction. Mesh-based chip multiprocessors. Noncontiguous processor. Router pipeline stages. Allocation mechanisms. Power reduction. Network routing. |
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