Sharif Digital Repository

Dark silicon and the history of computing

Author

Lotfi Kamran, P.

Publisher

Academic Press Inc,

Pub. Year

2018

Subjects

Dark silicon. / Denard scaling. / Moore's law. / Multicore processors. / Power management.

Temporal prefetching

Author

Lotfi-Kamran, P.

Publisher

Academic Press Inc,

Pub. Year

2021

Subjects

Temporal prefetching. / ISB. / STMS. / Cache. / Temporal correlation.

Spatial prefetching

Author

Lotfi Kamran, P.

Publisher

Academic Press Inc,

Pub. Year

2021

Subjects

Spatial. / Prefetching spatial correlation. / Cache. / SMS. / VLDP.

Preface

Author

Lotfi Kamran, P.

Publisher

Academic Press Inc,

Pub. Year

2022

Temporal prefetching

Author

Lotfi-Kamran, P.

Publisher

Academic Press Inc,

Pub. Year

2022

Subjects

Cache. / ISB. / STMS. / Temporal correlation. / Temporal prefetching.

Spatial prefetching

Author

Lotfi Kamran, P.

Publisher

Academic Press Inc,

Pub. Year

2022

Subjects

Cache. / SMS. / Spatial correlation. / Spatial prefetching. / VLDP.

An efficient hybrid-switched network-on-chip for chip multiprocessors

Author

Lotfi Kamran, P.

Publisher

IEEE Computer Society

Pub. Year

2016

Subjects

Adaptive systems. / Delay circuits. / Integrated circuit interconnects. / Mesh generation. / Multiprocessing systems. / Reconfigurable hardware. / Servers. / Switching circuits. / VLSI circuits. / Chip multi-processors (CMPs) / Chip Multiprocessor. / Circuit switching. / Interconnect fabrics. / Lastlevel caches (LLC) / Low latency. / Many-core processors. / Network-on-chip(NoC)

Near-Ideal networks-on-chip for servers

Author

Lotfi Kamran, P.

Publisher

IEEE Computer Society,

Pub. Year

2017

Subjects

Latency. / Server. / Computer architecture. / Network architecture. / Quality of service. / Resource allocation. / Routers. / Servers. / Supercomputers. / Key characteristics. / Lastlevel caches (LLC) / Low-latency networks. / Many-core processors. / Multihop networks. / Server processors. / State of the art. / Network-on-chip.

Evaluation of hardware data prefetchers on server processors

Author

Bakhshalipour, M.

Publisher

Association for Computing Machinery,

Pub. Year

2019

Subjects

Data prefetching. / Server processors. / Spatio-temporal correlation. / Economic and social effects. / Data pre-fetching. / Data-prefetching techniques. / High performance processors. / Scale-out workloads. / Server applications. / Spatiotemporal correlation. / Target architectures. / Cache memory.

Bingo spatial data prefetcher

Author

Bakhshalipour, M.

Publisher

Institute of Electrical and Electronics Engineers Inc,

Pub. Year

2019

Subjects

Big-Data Applications. / Data Prefetching. / Memory System. / Spatial Correlation. / Big data. / Dynamic random access storage. / Supercomputers. / Big data applications. / Data pre-fetching. / Efficient designs. / High probability. / Memory systems. / Spatial correlations. / Spatial patterns. / State of the art. / Memory architecture.

Blenda: dynamically-reconfigurable stacked DRAM

Author

Bakhshalipour, M.

Publisher

IEEE,

Pub. Year

2024

Subjects

3D Integration. / Die-Stacked DRAM. / DRAM Cache. / HBM. / Hybrid Memory Systems. / In-Package DRAM. / Cache memory. / Memory architecture. / Reconfigurable architectures.

Cache replacement policy based on expected hit count

Author

Vakil Ghahani, A.

Pub. Year

2017

Subjects

Belady's MIN. / Correlation. / last-level cache. / Memory system. / memory-intensive workload. / Correlation methods. / History. / Radiation detectors. / Last-level caches. / Memory systems. / Multi-core processing. / Prefetching. / Proposals. / Replacement policy. / Cache memory.

Cache replacement policy based on expected hit count

Author

Vakil Ghahani, A.

Publisher

Institute of Electrical and Electronics Engineers Inc,

Pub. Year

2018

Subjects

Belady's MIN. / Last-level cache. / Memory system. / Memory-intensive workload. / Correlation methods. / History. / Radiation detectors. / Last-level caches. / Memory systems. / Multi-core processing. / Prefetching. / Proposals. / Replacement policy. / Cache memory.

MANA: Microarchitecting a temporal instruction prefetcher

Author

Ansari, A.

Publisher

IEEE Computer Society,

Pub. Year

2022

Subjects

Costs. / Engines. / History. / Instruction cache. / Multicore processing. / Prefetching. / processors. / Program processors. / Cache memory. / Computer architecture. / Cost effectiveness. / Metadata. / Multicore programming. / Frontend bottleneck. / Instruction caches. / Instruction fetch. / Instruction prefetching. / Low-storage. / Multi-core processing. / Performance. / Processor. / Storage costs.

State-of-the-art data prefetchers

Author

Shakerinava, M.

Publisher

Academic Press Inc,

Pub. Year

2022

Subjects

BINGO prefetcher. / DOMINO prefetcher. / MLOP. / Multi-lookahead. / Offset prefetcher. / RUNAHEAD metadata.

Evaluation of data prefetchers

Author

Shakerinava, M.

Publisher

Academic Press Inc,

Pub. Year

2022

Subjects

Evaluation. / Methodology. / Multi-degree prefetching. / Offset prefetching. / Spatial prefetching. / Spatio-temporal prefetching. / Temporal prefetching.

MANA: Microarchitecting a temporal instruction prefetcher

Author

Ansari, A.

Publisher

IEEE Computer Society,

Pub. Year

2023

Subjects

Frontend bottleneck. / Instruction cache. / Instruction prefetching. / Processors.