Sharif Digital Repository

Evolution of sub-harmonic interfacial waves generated by a surface wave through a three-wave interaction

Author

Fazeli, M.

Pub. Year

2012

Subjects

Nonlinear effects. / Resonance. / Wave interaction. / Constant amplitude. / Experimental observation. / Explicit solutions. / Higher order. / Interfacial waves. / Nonlinear effect. / Rapid growth. / Steady state. / Subharmonics. / Three-wave interactions. / Three-wave resonant interaction. / Two layer fluid. / Wave flumes. / Wave interactions. / Wavebreaking. / Engineering. / Surface waves. / Amplitude. / Experimental study. / Nonlinearity. / Surface wave. / Theoretical study. / Wave breaking.

A survey on underwater wireless sensor networks routing algorithms

Author

Fazeli, M.

Publisher

Institute of Electrical and Electronics Engineers Inc,

Pub. Year

2018

Subjects

Engineering research. / Internet protocols. / Knowledge based systems. / Military applications. / Military communications. / Routing algorithms. / Surveys. / Underwater acoustics. / Environmental Monitoring. / Forwarding. / Low battery capacity. / Routing. / Underwater channels. / Underwater communication. / Underwater sensor networks. / Underwater wireless sensor networks. / Wireless sensor networks.

Molecular dynamics simulation of plastic deformation and interfacial delamination of NiTi/Ag bilayer by cyclic-nanoindentation: Effects of crystallographic orientation of substrate

Author

Fazeli, S.

Publisher

Elsevier B.V,

Pub. Year

2019

Subjects

Cyclic nanoindentation. / Deformation mechanisms. / Interfacial delamination. / Interfacial toughness. / Jarzynski's equality. / NiTi/Ag bilayer. / Binary alloys. / Energy dissipation. / Fracture mechanics. / Free energy. / Functional polymers. / Hardness. / Medical applications. / Molecular dynamics. / Molecular orientation. / Nanoindentation. / Plastic deformation. / Silver alloys. / Bi-layer. / Deformation mechanism. / Titanium alloys.

A power efficient masking technique for design of robust embedded systems against SEUs and SETs

Author

Fazeli, M.

Pub. Year

2008

Subjects

Delay elements. / Delay values. / Feedback line. / Masking technique. / Power efficient. / Single event transients. / Soft error. / Soft error rate. / Fault tolerance. / Fault tolerant computer systems. / Probability density function. / Quality assurance. / Transients. / Embedded systems.

Soft error rate estimation for combinational logic in presence of single event multiple transients

Author

Rajaei, R.

Pub. Year

2014

Subjects

Multiple event transient. / Single event multiple transient. / Single event multiple upset. / Single event transient. / Single event upset. / Soft error. / Error analysis. / Integrated circuits. / Microprocessor chips. / Monte Carlo methods. / Transients. / VLSI circuits. / Multiple events. / Single event. / Single event transients. / Single event upsets. / Single-event multiple-upset. / Radiation hardening.

Low cost soft error hardened latch designs for nano-scale CMOS technology in presence of process variation

Author

Rajaei, R.

Pub. Year

2013

Subjects

Combinational logic. / Low costs. / Nano-scale CMOS. / Process Variation. / Single event transients. / Soft error. / SPICE simulations. / Temperature variation. / CMOS integrated circuits. / Transients. / VLSI circuits. / Hardening.

Single Event Multiple Upset (SEMU) tolerant latch designs in presence of process and temperature variations

Author

Rajaei, R.

Publisher

World Scientific Publishing Co. Pte Ltd,

Pub. Year

2015

Subjects

Process and temperature variation. / Single event multiple effect. / Soft error tolerant latch. / Digital storage. / Flash memory. / Flip flop circuits. / High electron mobility transistors. / Radiation hardening. / Sensitivity analysis. / Temperature. / Temperature distribution. / Multiple effect. / Single event transients. / Single event upsets. / Soft error. / Temperature variation. / Transients.

An energy efficient circuit level technique to protect register file from MBUs and SETs in embedded processors

Author

Fazeli, M.

Pub. Year

2009

Subjects

Architectural vulnerability factor. / Average numbers. / Basic idea. / Cache size. / Circuit levels. / Clock gating techniques. / Embedded processors. / Energy efficient. / Low Power. / Low-power consumption. / Memory cell. / Multiple bit upset. / Power overhead. / Read operation. / Register files. / Single event transients. / Single-bit. / Soft error. / Energy efficiency. / Microprocessor chips. / Transients.