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Modeling and Optimization of Backside Power Delivery

Zamani, Majid | 2025

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 58864 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Sarvari, Reza
  7. Abstract:
  8. With the continued downscaling of transistor dimensions in advanced technology nodes, allocating significant standard cell area to signal and power distribution lines seriously challenges chip scalability. This structural density has led to inevitable competition between signal and power distribution rails; where increasing the cross-section of power lines, although improving voltage drop, comes at the cost of increased signal delay and reduced circuit speed. Conversely, prioritizing signal lines jeopardizes the stability of the Power Delivery Network (PDN) and degrades overall chip efficiency. Furthermore, the increasing complexity of early layers necessitates highly precise and costly lithography processes. To address these limitations, the Backside Power Delivery Network (BSPDN) architecture has been proposed as a transformative solution. This dissertation presents a comprehensive analysis of three prominent topologies. The primary innovation lies in the transition from traditional metals, such as Tungsten, to a proposed hybrid structure based on Ruthenium (Ru) and Molybdenum (Mo). Results indicate that utilizing this combination, while controlling the voltage drop within the allowable 5% margin of the supply voltage, significantly enhances stability against detrimental electromigration. Subsequently, the behavior of the power distribution network is examined in two distinct scenarios: with the voltage regulator positioned inside versus outside the package. Findings suggest that deploying the converter within the package, due to its active nature and feedback loop, reduces parasitic path effects and provides isolation for subsequent stages. Additionally, by integrating Metal-Insulator-Metal (MIM) capacitors into the network structure, Power Supply Noise (PSN) is effectively attenuated, ensuring chip stability; consequently, in the final optimized structure, the power supply noise for PV, BPR, and BSC topologies has been reduced by 61.4%, 16.8%, and 60.3%, respectively
  9. Keywords:
  10. Electromigration ; Pressure Drop ; Backside Power Delivery Network (BPDN) ; Power Supply Noise (PSN)

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