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Design and Implementation of a High-Speed, High-Efficiency Integrated DC–DC Converter

Kargaran, Masoud | 2026

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  1. Type of Document: Ph.D. Dissertation
  2. Language: Farsi
  3. Document No: 58797 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Medi, Ali
  7. Abstract:
  8. Design and Implementation of a High-Speed, High-Efficiency Integrated DC–DC ConverterWith the rapid development of portable electronic devices, systems-on-chip (SoCs), and high-density integrated circuits, the design and development of voltage regulators and DC–DC converters with high response speed, high efficiency, and minimal area occupation have become increasingly important. In such systems, digital or analog loads with fast current variation rates impose significant stress on power management units (PMUs), and if the regulator exhibits slow dynamic performance, voltage fluctuations may disrupt the proper operation of the entire system. In particular, in applications such as Dynamic Voltage Scaling (DVS), the fast response of the regulator directly affects system performance and battery lifetime. Considering these challenges, this dissertation focuses on the design, analysis, and implementation of two innovative structures in the field of low-dropout (LDO) voltage regulators and switching power converters. In the first part, a synchronous buck converter with an analog multiplier-based controller (AMC) is designed, demonstrating significantly faster performance compared to conventional structures. By utilizing an analog multiplier and a newly proposed residual-time generator structure, this converter stabilizes the output voltage within only two switching clock cycles. Based on measurement results, the regulator settles within 2 to 2.3 microseconds in response to a 1.3 A load step. Other notable features of this design include high energy efficiency (96%) and a high output current density of 1.38 A/mm². This regulator is suitable for applications that simultaneously require fast response, low power consumption, and compact design, and its synchronous structure also enables its use in noise-sensitive systems. In the second part of the dissertation, a novel ultra-fast LDO regulator structure with a resettable oscillator-based controller (ROR) is proposed. In this method, a very fast feedback loop is combined with an internal oscillator that continuously resets the intermediate nodes of the feedback loop to prevent loop oscillation while providing a rapid response to load and reference voltage step changes. This proposed structure can be considered a new category alongside emerging classes of fast-response LDO regulators with switching-based controllers, offering improved response time compared to other categories. According to measurement results, this regulator is capable of providing a dynamic response of less than 30 ns for a 400 mA load step in the presence of a 50 pF output capacitor. Furthermore, due to its low bias current consumption of 130 µA and small active area of 0.08 mm², this structure is well suited for implementation in systems with power and space constraints. Overall, the innovations presented in this dissertation—proposing fast control structures, optimizing power consumption, and reducing chip area—can serve as practical solutions for designing high-speed and compact regulators and converters in modern systems
  9. Keywords:
  10. High Efficiency ; Direct Current to Direct Current (DC to DC)Converters ; Power Management ; Resetting Oscillator Regulator ; Synchronous DC–DC Voltage Converter ; Fast Transient Response ; Analog Multiplier

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