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Efficient collaborative rule caching through pairing of P4 switches in SDNs
516 viewed

Efficient collaborative rule caching through pairing of P4 switches in SDNs

Saberi, M

Efficient collaborative rule caching through pairing of P4 switches in SDNs

Saberi, M ; Sharif University of Technology | 2024

516 Viewed
  1. Type of Document: Article
  2. DOI: 10.1109/GLOBECOM52923.2024.10901534
  3. Publisher: 2024
  4. Abstract:
  5. Software-defined networks (SDNs) provide customizable traffic control by storing numerous rules in on-chip memories with minimal access latency. However, the current on-chip memory capacity falls short of meeting the growing demands of SDN control applications. While rule eviction and aggregation strategies address this challenge at the switch level, programmable data planes enable a more flexible approach through cooperative rule caching. However, current solutions rely on computationally intensive off-the-shelf solvers to perform rule placement across the network. In this paper, we present an efficient solution for the cooperative rule caching problem. We first present the design of a resource-efficient switch capable of caching rules for its neighbors alongside a lightweight protocol for retrieving cached rules. Then, we introduce RaSe, an approximation algorithm for minimizing rule lookup latency across the network through optimized cooperation-aware rule placement. We conduct a theoretical analysis of RaSe, followed by a P4-based proof-of-concept assessment in Mininet and a large-scale numerical evaluation using real-world network topology. In comparison with existing solver-based solutions, the proposed method obtains the solution 160 times faster and improves the average rule lookup latency by about 21% compared to several algorithmic baselines. © 2024 IEEE
  6. Keywords:
  7. Approximation algorithm ; Data plane ; Optimization ; Software-defined networks ; Cache memory ; Internet protocols ; Minimization of switching nets ; 'Current ; Collaborative rule ; Data planes ; Data-plane ; Lookup latency ; On-chip-memory ; Optimisations ; Rule caching ; Switch cooperation ; Approximation algorithms
  8. Source: Proceedings - IEEE Global Communications Conference, GLOBECOM ; 2024 , Pages 1906-1911 ; 23340983 (ISSN); 979-835035125-5 (ISBN)
  9. URL: https://ieeexplore.ieee.org/document/10901534