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Exploiting direct memory operands in GPU instructions

Mohammadpur Fard, A ; Sharif University of Technology | 2024

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  1. Type of Document: Article
  2. DOI: 10.1109/LCA.2024.3371062
  3. Publisher: 2024
  4. Abstract:
  5. GPUs are widely used for diverse applications, particularly data-parallel tasks like machine learning and scientific computing. However, their efficiency is hindered by architectural limitations, inherited from historical RISC processors, in handling memory loads causing high register file contention. We observe that a significant number (around 26%) of values present in the register file are typically used only once, contributing to more than 25% of the total register file bank conflicts, on average. This paper addresses the challenge of single-use memory values in the GPU register file (i.e. data values used only once) which wastes space and increases latency. To this end, we introduce a novel mechanism inspired by CISC architectures. It replaces single-use loads with direct memory operands in arithmetic operations. Our approach improves performance by 20% and reduces energy consumption by 18%, on average, with negligible (<1%) hardware overhead. © 2002-2011 IEEE
  6. Keywords:
  7. RISC ; Computer graphics ; Computer hardware ; Energy utilization ; Memory architecture ; Program processors ; Reduced instruction set computing ; Arithmetic ; CISC ; Data parallel ; Diverse applications ; GPGPU ; Hardware ; Parallel task ; Register ; Register files ; Single use ; Graphics processing unit
  8. Source: IEEE Computer Architecture Letters ; Volume 23, Issue 2 , 2024 , Pages 162-165 ; 15566056 (ISSN)
  9. URL: https://ieeexplore.ieee.org/document/10460112