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  1. A symmetrical fully-integrated CMOS doherty power amplifier

A symmetrical fully-integrated CMOS doherty power amplifier

Ebazadeh, S ; Sharif University of Technology | 2024

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  1. Type of Document: Article
  2. DOI: 10.1016/j.mejo.2024.106188
  3. Publisher: 2024
  4. Abstract:
  5. This paper presents a new method to enhance the efficiency of a symmetrical doherty power amplifier (DPA) by fully utilizing the current driving capability of a class-C biased peaking amplifier. In this method, with utilization of the passive voltage gain concept, the input matching networks are designed in a way that the peaking path experiences a higher voltage gain than the carrier path, at high powers. As a result, the higher drive voltage of the peaking amplifier compensates for its lower gate bias and identical peak output currents for both amplifiers can be achieved. For demonstration purpose, a two-stage symmetrical DPA with a power utilization factor (PUF) of about unity is designed and fabricated in a standard 0.18-μm CMOS technology. The measurement results at 2.6 GHz show a power gain of 21 dB and an 1 dB compression point of 21.3 dBm. The peak power added efficiency (PAE) is 35% and the PAE at 6 dB power back-off (PBO) is better than 23%. © 2024 Elsevier Ltd
  6. Keywords:
  7. CMOS ; Doherty power amplifier (DPA) ; Passive voltage gain ; Peaking current ; Power back off (PBO) ; C (programming language) ; CMOS integrated circuits ; Doherty amplifiers ; Gain measurement ; 'current ; CMOS ; Doherty power amplifier ; Passive voltage ; Passive voltage gain ; Peaking current ; Power back off ; Power backoff ; Voltage gain ; Efficiency
  8. Source: Microelectronics Journal ; Volume 148 , 2024 ; 09598324 (ISSN)
  9. URL: https://www.sciencedirect.com/science/article/abs/pii/S0026269224001009