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An Efficient Architecture for ReRAM-based DNN Hardware Accelerator

Matin Yousefzade | 2025

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  1. Type of Document: M.Sc. Thesis
  2. Language: Farsi
  3. Document No: 57973 (19)
  4. University: Sharif University of Technology
  5. Department: Computer Engineering
  6. Advisor(s): Sarbazi Azad, Hamid
  7. Abstract:
  8. With the high accuracy of deep neural networks, these models are now widely used in applications such as machine vision, natural language processing, and medicine. Since implementing deep neural networks faces many challenges, such as high computational demands and the need for extensive memory accesses, the design and deployment of hardware accelerators for running these models have become increasingly attractive. With the development of prototype ReRAMs, some researchers have focused on designing ReRAM-based accelerators to execute deep neural network models with high speed and low energy consumption. In general, we categorize these accelerators into two categories, fixed-weight and non-fixed-weight, while both suffer from low utilization. The first category has low utilization and low scalability due to the writing all weights into the chip, while the second category suffers from low utilization, low accuracy, and high energy consumption due to the repeated reading of weights from main memory and their repeated writing into the ReRAM cells. In this study, to address the challenges of utilization, scalability, accuracy, and energy consumption, we propose a new architecture that utilizes a novel crossbar structure with cells capable of unlimited rewriting. According to the simulations performed, this architecture can improve utilization up to 92.5% and increase computational density up to 12.3x. It is worth mentioning that the enhancements achieved come at the expense of higher power consumption, which is entirely reasonable, given the significant improvement in utilization
  9. Keywords:
  10. Deep Neural Networks ; Hardware Accelerator ; In-Memory Computing ; ReRAM

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