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Error detection enhancement in PowerPC architecture-based embedded processors

Fazeli, M ; Sharif University of Technology | 2008

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  1. Type of Document: Article
  2. DOI: 10.1007/s10836-007-5017-3
  3. Publisher: 2008
  4. Abstract:
  5. This paper presents a behavior-based error detection technique called Control Flow Checking using Branch Trace Exceptions for PowerPC processors family (CFCBTE). This technique is based on the branch trace exception feature available in the PowerPC processors family for debugging purposes. This technique traces the target addresses of program branches at run-time and compares them with reference target addresses to detect possible violations caused by transient faults. The reference target addresses are derived by a preprocessor from the source program. To enhance the error detection coverage, three other mechanisms, i.e., Machine Check Exception, System Trap Instructions and Work Load Timer are combined with the Branch Trace Exception mechanism. The proposed technique is experimentally evaluated on a 32-bit PowerPC microcontroller using software implemented fault injection (SWIFI) and Power Supply Disturbances fault injection (PSD). A total of 6,000 faults were injected in microcontroller to measure the error detection coverage of the proposed control flow checking technique. The experimental results show that this technique detects about 95.2% of transient errors in software implemented fault injection method and 96.4% of transient errors in power supply disturbances fault injection method. © 2007 Springer Science+Business Media, LLC
  6. Keywords:
  7. Error detection ; Fault tolerant computer systems ; Microcontrollers ; Program debugging ; Program processors ; Control Flow Checking ; Transient faults ; Embedded systems
  8. Source: Journal of Electronic Testing: Theory and Applications (JETTA) ; Volume 24, Issue 1-3 , 2008 , Pages 21-33 ; 09238174 (ISSN)
  9. URL: https://link.springer.com/article/10.1007%2Fs10836-007-5017-3