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Efficient Circuit and Systematic Design of Successive Approximation Register Analog to Digital Converters

Khorami, Ata | 2020

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  1. Type of Document: Ph.D. Dissertation
  2. Language: Farsi
  3. Document No: 52840 (05)
  4. University: Sharif University of Technology
  5. Department: Electrical Engineering
  6. Advisor(s): Sharifkhani, Mohammad
  7. Abstract:
  8. Successive Approximation Register (SAR) Analog to Digital Converter (ADC) converts an analog signal to a digital code based on binary search. In contrast to other converters, such as Pipeline and Flash ADCs, most of the SAR ADC components are digital, hence, SAR ADC is technology scalable. Therefore, designed using smaller tehcnologies, SAR ADCs are able to operate at a higher frequency with a lower power consumption and area. The main focus of this thesis is to reduce power consumption, although the proposed techniques and circuits are able to improve other features such as precision, area, or speed.Considering Digital to Analog Converter (DAC), a low-power structure and a novel method to improve the precision of C2C DAC are proposed. Moreover, stepwise charging is proposed to reduce the power consumption. To do that, first a characterization method for stepwise adiabatic circuits is proposed. Then, two novel stabilizing switching techniques are proposed and characterized using the proposed method which make it possible to employ stepwise charging in different types of capacitive digital to analog converters.About comparator, several methods are proposed to reduce power consumption and enhance precision. Also, some of the proposed circuits are able to increase the speed of comparators. The proposed comparators are able to increase the speed by 50% and reduce the power or offset voltage by more than 50%. Regarding digital control circuit of SAR ADC, some methods are proposed to reduce power consumption. First, a systematic method is proposed for the digital controller and any digital circuit in general which is able to considerably reduce the leakage current. This method is able to reduce the leakage power in low-power low-speed ADCs by about 40% or 60%. After this, three low-power low-area or high-speed flip-flops are proposed which are efficient for SAR ADCs. These flip-flops are able to deliver comparable speed with the conventional flip-flop while consuming a lower power. One of them is able to considerably reduce the area and clock capacitive load in addition to delivering a lower power consumption
  9. Keywords:
  10. Digital to Analog Converter ; Flip Flop ; Successive Approximation Register (SAR) ; Analog to Digital Converter ; Low Power Comparator ; Leakage Current Reduction ; Low Power Consumption ; Stepwise Charging

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