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A scalable offset-cancelled current/voltage sense amplifier

Attarzadeh, H ; Sharif University of Technology | 2010

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  1. Type of Document: Article
  2. DOI: 10.1109/ISCAS.2010
  3. Publisher: 2010
  4. Abstract:
  5. the application of current sense amplifiers in scaled SRAM design is limited by two factors: the DC offset due to the device mismatch and limited voltage headroom. The presented scheme reduces the effect of offset by proposing an extra phase for offset cancellation before current sensing takes place. A twofold reduction of the cell access time is achieved compared to the conventional scheme under similar cell current and bitline capacitance. The offset cancellation phase takes place in parallel to the wordline decoding time in order to speed up the current sensing. The proposed scheme requires a small power budget due to a self shut off mechanism. In addition to presenting a comparison with the conventional schemes, the efficiency of the proposed scheme is evaluated in 90nm, 130nm and 180nm CMOS technologies to show the scalability and the robustness of the proposed scheme under smaller voltage headroom
  6. Keywords:
  7. Access time ; Bitline capacitance ; Cell current ; CMOS technology ; Conventional schemes ; Current sense amplifiers ; Current sensing ; DC offsets ; Device mismatch ; Offset cancellation ; Power budgets ; Sense amplifier ; Speed-ups ; SRAM design ; Two-fold reduction ; Wordlines ; CMOS integrated circuits ; DC power transmission ; Dynamic random access storage ; Fabrics ; Logic design ; Static random access storage
  8. Source: ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, 30 May 2010 through 2 June 2010, Paris ; 2010 , Pages 3853-3856 ; 9781424453085 (ISBN)
  9. URL: http://ieeexplore.ieee.org/document/5537701