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  1. Dynamically adaptive register file architecture for energy reduction in embedded processors

Dynamically adaptive register file architecture for energy reduction in embedded processors

Khavari Tavana, M ; Sharif University of Technology | 2015

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  1. Type of Document: Article
  2. DOI: 10.1016/j.micpro.2015.01.005
  3. Publisher: Elsevier , 2015
  4. Abstract:
  5. Energy reduction in embedded processors is a must since most embedded systems run on batteries and processor energy reduction helps increase usage time before needing a recharge. Register files are among the most power consuming parts of a processor core. Register file power consumption mainly depends on its size (height as well as width), especially in newer technologies where leakage power is increasing. We provide a register file architecture that, depending on the application behavior, dynamically (i) adapts the width of individual registers, and (ii) puts partitions of temporarily unused registers into low-power mode, so as to save both static and dynamic power. We show that our scheme increases register file area by 3.6% and imposes 2.85% performance overhead on average. Our experimental results on OpenRISC 1200 processor and with selected MiBench benchmark suite show up to 29%, and 54% (24% and 49% on average) reduction in dynamic and static energy consumption of the register file, respectively
  6. Keywords:
  7. Computer architecture ; Energy efficiency ; Energy utilization ; Application behaviors ; Benchmark suites ; Embedded processors ; Energy reduction ; Low Power ; Processor architectures ; Register files ; Unused registers ; Embedded systems
  8. Source: Microprocessors and Microsystems ; Volume 39, Issue 2 , March , 2015 , Pages 49-63 ; 01419331 (ISSN)
  9. URL: http://www.sciencedirect.com/science/article/pii/S014193311500006X