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  3. A low-power 10-Bit 40-MS/s pipeline ADC using extended capacitor sharing
A low-power 10-Bit 40-MS/s pipeline ADC using extended capacitor sharing
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A low-power 10-Bit 40-MS/s pipeline ADC using extended capacitor sharing

Esmaeelzadeh, H

A low-power 10-Bit 40-MS/s pipeline ADC using extended capacitor sharing

Esmaeelzadeh, H ; Sharif University of Technology

782 Viewed
  1. Type of Document: Article
  2. DOI: 10.1109/ISCAS.2014.6865343
  3. Abstract:
  4. This paper describes a new capacitor sharing technique for pipeline ADCs. It enables power reduction of the first and second MDACs simultaneously. The presented noise and power analysis shows that the proposed method is about 30% more efficient than the conventional one in terms of the first and second MDACs power dissipation. A 10-bit 40MS/s pipeline ADC employing the proposed technique was designed in 90-nm CMOS technology achieving a power consumption of 4.2 mW
  5. Keywords:
  6. Capacitors ; CMOS integrated circuits ; 90-nm cmos ; Low Power ; Pipeline ADCs ; Power analysis ; Power reductions ; Pipelines
  7. Source: Proceedings - IEEE International Symposium on Circuits and Systems ; 1- 5 June , 2014 , pp. 1147-1150 ; ISSN: 02714310
  8. URL: http://ieeexplore.ieee.org.ezp2.semantak.com/xpl/articleDetails.jsp?arnumber=6865343