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Designing best effort networks-on-chip to meet hard latency constraints

Seiculescu, C ; Sharif University of Technology

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  1. Type of Document: Article
  2. DOI: 10.1145/2485984.2485996
  3. Abstract:
  4. Many classes of applications require Quality of Service (QoS) guarantees from the system interconnect. In Networks-on-Chip (NoC) QoS guarantees usually translate into bandwidth and latency constraints for the traffic flows and require hardware support in the NoC fabric and its interfaces. In this article we present a novel NoC synthesis framework to automatically build networks that meet hard latency constraints of end-to-end traffic streams without requiring specialized hardware for the network components. The hard latency constraints are met by carefully designing the NoC topology and selecting the appropriate routes for flow using lean best-effort network components. We perform experiments on several System on Chip (SoC) benchmarks. We compared against a topology synthesis method with no support for real-time constraints and we show that the proposed method can produce topologies that can meet significantly tighter worst case latency constraints (on average 44%).We also show that the tightest worst case latency can be provided with little overhead on power consumption (on average 8.5%)
  5. Keywords:
  6. NoC ; Topology ; Worst case latency ; Best effort networks ; Latency constraints ; Quality of service (QoS) guarantees ; Real time constraints ; Specialized hardware ; Topology synthesis ; Computer hardware description languages ; Hardware ; Microprocessor chips ; Network components ; Telecommunication networks ; Quality of service
  7. Source: Transactions on Embedded Computing Systems ; Vol. 12, issue 4 , June , 2013 ; ISSN: 15399087
  8. URL: http://dl.acm.org/citation.cfm?id=2485996