Exploring Emerging Memory Technologies and 3D Die-stacking for Power/Thermal-friendly Fast-memory Architectures

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Jalili, Majid | 2013

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Type of Document: M.Sc. Thesis
Language: Farsi
Document No: 44723 (19)
University: Sharif University of Technology
Department: Computer Engineering
Advisor(s): Sarbazi Azad, Hamid
Abstract:
As feature size of transistors in deep sub-micron technologies decreases, serious problems emerge in term of scalability, power consumption and memory access latency. A new approach to mitigate these drawbacks is to use non-volatile memory as probable alternative. Among different alternatives, Phase Change Memories (PCMs) are more likely to be used in place of conventional memories. Since fabricating PCM with 2D fashion design is a high-cost process, 3D integration is known as a good candidate solution according to its fabrication process flexibility. In 3D ICs, the increase in power density leads to elevated on-chip temperature that results in large reduction of read and write power consumption; and more importantly make PCM system susceptible to resistance drift soft errors. In this thesis, a time and temperature aware memory architecture has been proposed to facilitate resistance drift confronting. Full-system simulation results show 20% reduction in read-out error and up to 73% energy saving alongside 3% improvement in CPI compared to our baseline
Keywords:
On-Chip Multiprocessor ; Three Dimensional Integration ; Phase Change Memory ; Resistance Drift

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