Sharif Digital Repository

Security protocols are mostly verified using tools based on model checking approach. These tools are automatic but they can be used for verifying protocols with low complexity and limited number of participants. The other approach that can be used in these cases is theorem proving. Inductive method is a theorem proving approach which is based on induction in mathematics. Inductive method has been applied for verifying several classical and real-world protocols.
The basic concepts in this method are event and trace. Using the concept of event, the network traffic can be modeled through various events occurring in the network. Atrace is a list of events and model a history of the network.... 

While digital IC technology scales down, the impact of size effects in copper interconnects become more important because wire dimensions reach the same order of electron mean free path yielding increased resistivity of metal due to surface and grain boundary scatterings. Hence, because of their longer MFP, Carbon nanotubes are proposed as potential candidates for replacing copper interconnects. Furthermore, wires, especially power and ground lines, are becoming more and more vulnerable to electromigration because of rapid grows in current densities which increases the temperature of IC and interconnects as well. Sub-ambient cooling has long been suggested for improving the performance of... 

Recently, the size of copper interconnects is going to reach lower than the mean free path of electrons for copper. In this situation, we should consider the effect of other scattering mechanisms as well as thermal scattering on copper thin films. In this work we study both DC size effect and anomalous skin effect on resistivity by a Monte Carlo method. Contribution of each scattering mechanism and the interaction between them are analyzed separately. The structure of electrical field and distribution of current in thin films have also been studied. Investigating of the effect of exact nature of surface scattering and grain boundary scattering on resistivity is one of the interests of this... 

In this thesis, the simulation of HEMT for high frequency applications has been explored. It has been tried to examine the changes such as: gate recess, T-shaped gate, changing the channel length and doping of buffer layer on the performance of the proposed device. Simulation results show that the best way to improve the device performance, in particular its cut-off frequency, is increase in buffer layer doping density. Because it significantly increase the saturation current, electron mobility inside the channel, the transconductance and the cut-off frequency. If we need to lower the noise, the T-shaped gate can also be used. Also, by change in doping of donor layer, amount of 1017 cm-3 is... 

The exponential increase in power density within a chip due to higher frequency of operation in recent years (Moor's law) is a major limiting factor for designers. Increasing the number of parallel cores instead of increasing the frequency of operation is a possible solution. The design of connections within the cores can be followed by the old process but the global interconnectsbetween the cores instead of point to point can be replaced byNetwork-on-Chip (NoC). In this thesis, The dimensions of global interconnects in many-core chips are optimized for maximum bandwidth density and minimum delay taking into account network-on-chip router latency and size effects of coppe. The optimal... 

Delay of Interconnects in modern digital ICs is several times greater than delay of gates. One proper measure for this problem is to shorten interconnects length by using three dimensional structures instead of conventional two dimensional structures. In these structures TSVs (Through Silicon Vias) make connection between stratums. Power integrity in 3D ICs necessitates power distribution networks to have minimum IR drop and Ldi/dt noise. In this dissertation we design power distribution network considering IR drop and Ldi/dt noise margin. We expand a mathematical model which represents differential equation of power distribution in the surface of each stratum. Using this expanded model we... 

Several advantages and problems associated with technology scaling. One of the most important problems facing technology scaling is interconnects. As technology scales down wire delay becomes dominant. Optical interconnects has been subject of many researches for more than two decades to overcome this problem. The key idea behind near speed of light transmission (NSoLT) is that for buffers at the end of ITRS projections input capacitances could be as small as tens of atto Farads. Hence, voltage of the end of global wires could jump at the time of flight.
In this project, a global wire has been divided in to k segments in a way that data can be transferred with the speed close to the... 

As the transistors’ dimensions in integrated circuits shrink, according to Moore’s law, a number of challenges emerges that can decrease the benefits of scaling. One of the main challenges in deep submicron CMOS technologies is the delay in interconnects. In recent years, researchers have been looking into different methods to minimize the delay in interconnects. International Technology Roadmap for Semiconductors (ITRS) predicts that the input capacitance of a buffer will become in the order of 10s of aFs with technology scaling. This will give us the opportunity to transmit the data in electrical interconnects near the speed of light.In this thesis, a novel buffer is designed in which the... 

Since interconnects are playing a very important role in today’s IC technology, introducing new models and approximations is vital to IC designers. In this dissertation, maxwell equations are introduced as they are the main equations governing transmission lines. Different methods to model interconnects are also presented. Moreover, because of the importance of the step response of a system, available methods for finding the step response of interconnects are briefly discussed. Some approximations are also described, which result in faster but not very accurate responses. Delay and noise in integrated circuit connections have been the subject of several investigations for a long time. Since... 

Due to the growth of information volume and increment in the speed of processor units, it is critical to achieve higher speed in data transaction systems. This necessity could be recognized in all fields, from digital data transactions on a chip and among its building blocks to data transactions among electronic boards and computerized systems in huge control constructions.
Methods of data transmission have been improved both in terms of speed and simplicity for different applications in today’s enormous consumer electronics market. One possible option is to use conventional wires as physical channel of transmission system.
The most important drawback of the wires is their relative... 

Today, the internal connections of the CPUs with a few billion wired transistors in 14 copper layers on the silicon wafer are possible. Recently, power dissipation has slowed the growth rate of clock growth in CPUs, and nowadays sometimes more than 60% power is lost in connections. In this situation, the increase in efficiency has been achieved in accordance with Moore's law with multi-core chips. This theme has made the connections between the cores much more important than before. Usually the information in the network structure on chip (NOC) is transmitted on these connections. Therefore, all three aspects of delay, power dissipation and bit rate are important for communication channels.... 

The process of contracting the chips will lead the increasing of impurity concentration, decreasing the bias voltage and threshold voltage to make stable the electrical field. For using the advantage of lesser dimensions of the total circuit using decreasing bias voltage lead the dimension of the wires to be decrease also. Therefore, once the parasitic effects of wires, the RC delays of wires and the noise of power transmission will enhance obviously. With this contracting by process, electrical resistance of interconnect will enhance also. The reason of this matter is that the area chip will decrease significantly. While the operational frequency increases the effect of inductance should be... 

Turbulent combustion at supercritical condition have a considerable effect in modern high performance rocket propulsion systems, gas turbines and diesel engines. In such a reaction conditions, an abrupt changes occur in thermodynamics and transport properties of fluid. So numerically modeling of a real fluid behavior of the cryogenic propellants and the turbulent trans-critical mixing and combustion processes faces serious challenges.In this study, in order to realistically represent turbulence–chemistry interactions, detailed chemical kinetics and real-fluid thermodynamic behaviors related to the gaseous hydrogen and cryogenic liquid oxygen combustion under supercritical pressures, the... 

The Technology scaling and reduction of the size of transistors has led to an increase in the switching speed and, as a result, to an increase in the clock frequency.But in recent years, the continuation of this process of increasing the clock frequency has been almost stopped considering the considerations of power consumption. Previous research has shown that approximately 30-50% of the dynamic power consumed by the microprocessor is wasted in the clock distribution network.Therefore, the design of clock distribution networks is a big challenge for future microprocessors due to the trend of Technology scaling and process variation. In this thesis, we used the emerging technology of... 

In advanced integrated circuits, the increasing number and length of interconnects lead to higher dynamic power dissipation. This power loss is mainly caused by switching activity and the large capacitive loading of interconnects. Reducing the interconnect capacitance is therefore considered one of the most effective approaches for improving performance and lowering power consumption in such circuits. In this research, the design and analysis of a ferroelectric-based transmission line employing negative capacitance are presented. The primary objective of this work is to investigate the impact of utilizing ferroelectric materials operating in the negative-capacitance regime on reducing the... 

With the continued downscaling of transistor dimensions in advanced technology nodes, allocating significant standard cell area to signal and power distribution lines seriously challenges chip scalability. This structural density has led to inevitable competition between signal and power distribution rails; where increasing the cross-section of power lines, although improving voltage drop, comes at the cost of increased signal delay and reduced circuit speed. Conversely, prioritizing signal lines jeopardizes the stability of the Power Delivery Network (PDN) and degrades overall chip efficiency. Furthermore, the increasing complexity of early layers necessitates highly precise and costly...