Sharif Digital Repository

Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising alternative to SRAM in cache memories. However, STT-MRAMs face with high probability of write errors due to its stochastic switching behavior. To correct the write errors, Error-Correcting Codes (ECCs) used in SRAM caches are conventionally employed. A cache line consists of several codewords and the data bits are selected in such a way that the maximum correction capability is provided based on the error patterns in SRAMs. However, the different write error patterns in STT-MRAM caches leads to inefficiency of conventional ECC configurations. In this paper, first we investigate the efficiency of ECC configurations... 

The flexibility of software-based fault tolerant approaches in providing the required level of reliability Commer-cial-Off-The Shelf (COTS) devices made them the first choice in designing safety-critical systems. In this paper, we propose a reliability improvement method for COTS-based systems, so-called, RI-COTS. The main idea behind RI-COTS is to establish a tradeoff between reliability and performance of COTS system through controlling redundant execution at instruction level. RI-COTS is implemented on LEON2 processor VHDL model. Our simulation results show that comparing with the most related studies, RI-COTS can improve the fault detection capability by 20% with only 4% performance... 

Spin-transfer torque magnetic RAMs (STT-MRAMs) are the most promising alternative for static random-access memories in large last-level on-chip caches due to their higher density and near-zero leakage power. However, the reliability of STT-MRAMs is threatened by high probability of read disturbance and write failure. Both read disturbance and write failure, which cause a soft error in the cache cells, have an asymmetric behavior. Read disturbance occurs only in STT-MRAM cells storing '1' value, and write failure error rate in a → 1 transition is much higher than that in a 1 → 0 transition. In this paper, we propose Read/write Error-rate Aware Coding Technique (REACT) to improve the... 

Fog devices in fog computing frameworks are responsible for fetching and executing the tasks submitted by the deployed resource-constraint embedded edge devices. Based on the availability of resources, tasks are offloaded to the virtual machines hosted by the fog devices. These tasks may then get scheduled to guarantee a number of efficiency-related metrics. While throughput has a decisive impact on the timely execution of tasks, the appropriate utilization of this metric has not been considered in the existing mechanisms. In this letter, we first discuss the proper use of this objective in the fitness function of meta-heuristic algorithms. Then, we explain that adopting throughput by the... 

Scratchpad memory (SPM) is extensively used as the on-chip memory in modern embedded processors alongside of the cache memory or as its alternative. Soft errors in SPM are one of the major contributors to system failures, due to ever-increasing susceptibility of SPM cells to energetic particle strikes. Since a large fraction of soft errors occurs in the shape of Multiple-Bit Upsets (MBUs), traditional memory protection techniques, i.e., Error Correcting Code (ECCs), are not affordable for SPM protection; mainly because of their limited error coverage and/or their high overheads. This paper proposes a novel algorithm that efficiently protects SPM with high error correction capability and... 

Scratch Pad Memory (SPM) is an important part of most modern embedded processors. The use of embedded processors in safety-critical applications implies including fault tolerance in the design of SPM. This paper proposes a method, called FTSPM, which integrates a multi-priority mapping algorithm with a hybrid SPM structure. The proposed structure divides SPM into three parts: 1) a part is equipped with Non-Volatile Memory (NVM) which is immune against soft errors, 2) a part is equipped with Error-Correcting Code, and 3) a part is equipped with parity. The proposed mapping algorithm is responsible to distribute the program blocks among the above three parts with regards to their vulnerability... 

Recently, energy harvesting systems that utilize hybrid NVM-SRAM memory in their designs are introduced as a promising alternative for battery-operated systems. Since the ambient input power of an energy harvesting system fluctuates as the environmental conditions change, the system may stop the execution of programs until it receives enough energy to continue the execution. Resuming the execution of a program after the suspension may lead to data inconsistency in an energy harvesting system and threatens the correct functionality of the programs. In this paper, we propose COACH, an energy-efficient consistency-aware memory scheme which guarantees the correct functionality and consistency of... 

Recently, IoT has been massively applied in different areas of human life. Meanwhile, in many of the IoT applications, e.g., the remote patient health-care monitoring systems, the reliability of communications, and the consumed energy in IoT devices, which are mostly battery-operated, are very challenging. Since IoT devices are typically operated in lossy environments, providing a reliable transmission for the packets imposes a noticeable amount of energy consumption. In addition, the runtime movement of the IoT devices in mobile networks further intensifies these issues. Therefore, the applied policies in the IPv6 RPL as the standard routing mechanism in IoT networks, play an important role... 

The standardized IPv6 Routing Protocol for Low-power and Lossy Networks (RPL) has enabled efficient communications between thousands of smart devices, sensors, and actuators in a bi-directional, and end-to-end manner, allowing the connection of resource constraint devices in multi-hop IoT infrastructures. RPL is designed to cope with the major challenges of Low-power and Lossy Networks (LLNs), specifically their energy-efficiency. However, RPL is facing with severe congestion and load balancing problems, leading to a low Packet Delivery Ratio (PDR) in the network. For the first time since the declaration of RPL, in this paper we explain that ignoring the specifications of the reception and... 

In recent years, STT-RAMs have been proposed as a promising replacement for SRAMs in on-chip caches. Although STT-RAMs benefit from high-density, non-volatility, and low-power characteristics, high rates of read disturbances and write failures are the major reliability problems in STTRAM caches. These disturbance/failure rates are directly affected not only by workload behaviors, but also by process variations. Several studies characterized the reliability of STTRAM caches just for one cell, but vulnerability of STT-RAM caches cannot be directly derived from these models. This paper extrapolates the reliability characteristics of one STTRAM cell presented in previous studies to the... 

Spin-Transfer Torque Random Access Memories (STT-RAMs) are a promising alternative to SRAMs in on-chip caches. STT-RAMs face with a high error rate in write operations due to stochastic switching. To alleviate this problem, Error-Correcting Codes (ECCs) are commonly used, which results in a significant area and energy consumption overhead. This paper proposes an efficient technique, so-called Adaptive Way Allocation for Reconfigurable ECCs (AWARE), to correct write errors in STT-RAM caches. AWARE exploits the asymmetric error rate in cell switching directions, which leads to data-dependent write error rates, to reduce the ECC overheads without compromising the reliability of the cache. To... 

Due to serious problems of SRAM-based caches in nano-scale technologies, researchers seek for new alternatives. Among the existing options, STT-RAMseems to be themost promising alternative.With high density and negligible leakage power, STT-RAMs open a new door to respond to future demands of multi-core systems, i.e., large on-chip caches. However, several problems in STT-RAMs should be overcome to make it applicable in on-chip caches.High probability of write error due to stochastic switching is amajor problemin STT-RAMs. Conventional Error-CorrectingCodes (ECCs) impose significant area and energy consumption overheads to protect STT-RAMcaches. These overheads in multi-core processors with... 

Spin-Transfer Torque Random Access Memories (STT-RAMs) are a promising alternative to SRAMs in on-chip caches. STT-RAMs face with a high error rate in write operations due to stochastic switching. To alleviate this problem, Error-Correcting Codes (ECCs) are commonly used, which results in a significant area and energy consumption overhead. This paper proposes an efficient technique, so-called Adaptive Way Allocation for Reconfigurable ECCs (AWARE), to correct write errors in STT-RAM caches. AWARE exploits the asymmetric error rate in cell switching directions, which leads to data-dependent write error rates, to reduce the ECC overheads without compromising the reliability of the cache. To... 

With the recent development in Non-Volatile Memory (NVM) technologies, several studies have suggested using them as an alternative to SRAMs in on-chip caches. However, limited endurance of NVMs is a major challenge when employed in the caches. This paper proposes a data manipulation technique, so-called Wearout Informed Pattern Elimination (WIPE), to improve the endurance of NVM-based caches by reducing the activity of frequent data patterns. Simulation results show that WIPE improves the endurance by up to 93% with negligible overheads. © 2017 IEEE  

Energy consumption is a major challenge in IoT devices, which was aimed to be improved by employing energy-efficient objective functions (OFs) in the structure of the RPL routing protocol. Meanwhile, the majority of the existing OFs mainly perform the parent selection based on the gathered information from the routing layer. Nevertheless, based on our investigations, there exists a series of transmission operations in the medium access control (MAC) layer, which significantly affects the energy consumption in IoT devices. Therefore, in this article, we propose ELITE, an energy-efficient cross-layer OF, which introduces a novel routing metric, called strobe per packet ratio (SPR). SPR... 

Nowadays, leakage energy constitutes up to 80% of total cache energy consumption and tag array is responsible for a considerable fraction of static energy consumption. An approach to reduce static energy consumption is to replace SRAMs by STT-RAMs with near zero leakage power. However, a problem of an STT-RAM cell is its limited write endurance. In spite of previous studies which have targeted the data array, in this study STT-RAMs are used in the L1 tag array. To solve the write endurance problem, this paper proposes an STTRAM/SRAM tag architecture. Considering the spatial locality of memory references, the lower significant bitlines of the tag update more. The SRAM part handles the updates... 

Mobile portable embedded devices are becoming an integral part of our daily activities in the vision of Internet of Things (IoT). Nevertheless, due to lack of mobility support in the IPv6 routing protocol for low-power and lossy networks (RPLs), which is standardized for multihop IoT infrastructures, providing reliable communications in terms of packet delivery ratio (PDR) in mobile IoT applications has become significantly challenging. While several studies tried to enhance the adaptability of RPL to network dynamics, their utilized routing metrics have prevented them from establishing long-lasting reliable paths. Furthermore, the stochastic parent replacement policy in the standard version... 

Resource-limited mobile IoT networks are a dynamic, and uncertain wireless communicating system. In such systems, the standard RPL routing protocol cannot select long-lasting communication links due to not employing mobility-aware metrics, e.g., direction and speed of movements. While several classical heuristic approaches exist to improve PDR in RPL-based mobile networks, their solutions cannot adapt to alterations of the mobile topology. Hence, in this paper, by mapping the routing problem in mobile and resource-limited networks into an infinite-time horizon MDP, an energy-aware and reliable RPL-based routing mechanism based on Q-learning is proposed to improve PDR in mobile IoT networks.... 

Spin-transfer-torque RAMs (STT-RAMs) are the most promising technology for replacing Static RAMs (SRAMs) in on-chip caches. One of the major problems in STT-RAMs is the high error rate due to stochastic switching in write operations. Cache replacement algorithms have a major role in the number of write operations into the caches. Due to this fact, it is necessary to redesign cache replacement algorithms to consider the new challenges of STT-RAM caches. This paper proposes a cache replacement algorithm, which is called least error rate (LER) , to reduce the error rate in L2 caches. The main idea is to place the incoming block in a line that incurs the minimum error rate in write operation.... 

SRAM-based scratchpad memories (SPMs) used in embedded systems impose high leakage power. Designing SPMs based on non-volatile memories (NVMs) were proposed as NVMs have negligible leakage power. The main problem of utilizing NVMs across the SPM is their limited number of write cycles (endurance). This problem threatens the reliability of NVM-based SPMs. To alleviate the problem of limited endurance in NVM-based SPMs, this paper proposes a method, called overwrite purging through in-execution memory address snooping (OPTIMAS). The main idea behind the proposed method is to control the lifetime of NVM-based SPMs, directly by a hardware unit, outside of the SPM mapping algorithm. This idea...