Sharif Digital Repository

Behran Mehr Peyma (BMP) is an elevator equipment producer and trader in Iran which was established in 2004. At first they are producing some regular parts of elevator and then during these years they are trying to improve their work and expand their business till they have the 15% market share in elevator market in Tehran.In this thesis I am trying to use the SWOT and PETS methods to show the exact situation of BMP comparing to the whole market considering the competitors.During this reduction in the market I suggest to BMP to change some policies and use some of its strength to attract some new customers, changing their brand name and find a relation to contribute in some tenders and... 

Growth in the number of transistors on a single die has made Network-on-Chips more vulnerable to transient faults such as Crosstalks, SEUs and MBUs. The aim of this thesis is to evaluate the effects of virtual channel structures on the performance and the power consumptions of NoCs in the presence of transient faults. Evaluations have been carried out by different switch architectures and experimental conditions, i.e., different traffic and fault injection rates. In this regard, we have measured the power and latency of the switch both in different buffer allocation mechanisms and different switching methods. The evaluated switching methods in this work vary from Virtual Cut through (VCT) to... 

Nowadays, distributed embedded systems are extensively employed in safety-critical automotive applications, e.g. Steer-By-Wire and Brake-By-Wire. Moreover, according to the present and future needs of the automotive industry of Iran, in this Ph.D. thesis, fault tolerance in safety-critical distributed automotive communication networks has been improved. This thesis consists of three research layers. In the first layer, several comprehensive studies on all automotive communication protocols and their architectures have been done. Among the protocols, the FlexRay communication protocol has been selected to employ in safety-critical distributed embedded systems. In the second layer, the fault... 

The wide range of embedded processors and their reliance on nano-scale technologyhave brought them serious concerns on reliability, power consumption, timeliness and cost. Therefore, theseconcernsmust be addressed at the design process withemploying minimum facilities.This thesis proposes a low-cost concurrent error detection method based on control flow checking suitable for embedded processors. Most of the previous control flow checking methods either do not consider the embedded processors concerns, or they are not applicable to processors with on-chip cache memories.The key idea behind the proposed control flow checking method is to embed specific hardware components in the IP core of an... 

Energy consumption, area, reliability and predictability are the major concerns in embedded systems. Using scratchpad memories (SPMs) instead of cache memories has an increasing role to satisfy these limitations. SPM as an on-chip SRAM memory is highly vulnerable to soft errors and as it contains the most frequently used blocks of the program, errors in SPM can easily propagate in system leading to erroneous results. This thesis proposes two approaches to protect the SPM against soft errors. The first approach, MM-SPM, proposed to protect the instruction SPM and the second approach, CR-SPM, proposed to protect dynamically mapped data and instructions to the SPM. The main idea behind the... 

In recent years, the use of embedded processors has grown increasingly in wide range of computer systems; so that most of manufactured CPUs are used in emebedded systems many of which are safty-critical systems such as medical devices, aircraft flight control, space systems, nuclear systems, etc. The incidence of failure in these systems can cause irreversible damages on human life, financial or environmental matters. Silicon process technology trends, such as reducing the threshold voltage, increasing the frequency and decreasing the size of transistors, not only caused increase in single-bit fault rate but also caused occurance of multi-bit faults. Due to importance ofcorrect operation of... 

Nowadays, one of the most important challenges in the design of digital circuits is their susceptibility to the strike of high energy particles which leads to the Single Event Transient (SET) and Multiple Event Transients (MET). In fact, technology scaling which results in lower supply voltage, higher operating frequency, and lower nodal capacitance, makes today’s digital circuits more susceptible not only to high energy particles but also to low energy particles. Moreover emerging deep sub-micron technologies and the integration of more cells in today’s chips have caused higher probability of MET occurrences. A lot of research has tried to reduce the soft error rate due to high energy... 

Wireless Sensor Networks (WSNs) are prone to faults due to battery depletion of nodes, where a node failure can disturb routing, as it plays a key role in transferring sensed data to the end users. A WSN may be partitioned into groups of nodes called clusters; for every cluster, there is a node, called Cluster Head (CH) that is responsible for collecting and transferring data from all nodes in that cluster. This means that the CH is a single point of failure; i.e., once a CH fails, the whole cluster will fail, which leads to inability of its members for transferring data outside the cluster. This thesis presents a Fault-Tolerant and Energy-Aware algorithm (FTEA), which prolongs the lifetime... 

The increasing size of valuable data emphasizes the importance of applying reliability in storage systems. One way to protect storage system failures is using erasure codes. The advantages of using erasure codes are their low overheads and high reliability. Soft errors caused by high-energetic particles do not only corrupt data in the SSD-based storage systems, but also in the erasure codes. In this regards, it is important to protect erasure code implementations against soft errors. This thesis proposes a fault-tolerant implementation of erasure codes. The proposed method is based on the structure of each erasure code. This method is analytically evaluated on four erasure codes, i.e.... 

With continuous device down-scaling and increase in transistor counts on a chip, complementary metal-oxide-semiconductor (CMOS) technology has become extremely sensitive to soft errors. Soft errors are transient errors caused by energetic particles such as neutrons and alpha particles. An essential step to design a soft error tolerant digital system with minimal performance and power overheads is Soft Error Rate (SER) estimation of system components. Until recently, Single Event Upsets (SEUs) in latches and Filp-Flops (FFs) and Single Event Transients (SETs) in combinational logic parts of digital circuits were regarded as the main effects of particle strikes. However, with the emerging... 

The purpose of this study was to find out the effective factors on customer satisfaction and its consequences in Kish Island (IRAN).In this research the researcher had used two different kind of sample the first sample is customers of three different hotels of 3 star, 4 star, 5 star and The second sample are managers of these hotels. The sample size was 285 of hotel customers and 11 of hotel managers. The first purpose of this study was to identify the drivers and results of customer satisfaction and also identifying there relationship with customer satisfaction. The second goal of this study was to propose a customer satisfaction model for hotel industry in kish island (IRAN). In this... 

Ever increasing applications of embedded systems have motivated the designers to pay special attention to the design requirements of such systems. Among embedded applications, safety-critical systems have high reliability requirements as failures in such systems may endanger human life or result in catastrophic consequences. Embedded processors as the computation cores of embedded systems are very crucial from reliability point of view. This is because; a failure in the processor most probably leads to a system failure. One effective way to protect embedded processors against environmental faults is to use system level fault-tolerant techniques such as Master/Checker (M/C) or Triple Modular... 

Ever increasing applications of embedded systems have motivated designers to pay special atten-tion to the design requirements of such systems. Among embedded applications, safety-critical sys-tems have high reliability requirements as failures in such systems may endanger human life or re-sult in catastrophic consequences. Embedded processors as the computation cores of embedded systems are very crucial from reliability point of view. Reducing feature size, power supply voltage and also increasing operating frequency have increased the occurance rate of transient faults in such processors. Built in Self-Test facilities available in many of embedded systems forms about 70% of total cost in... 

Vulnerability of SRAM-based FPGAs to soft errors signals the importance of applying fault-tolerant methods in FPGAs used in safety-critical applications. Previous methods to protect SRAM-based FPGAs impose significant area and power overheads. Additionally, they suffer from susceptibility of configuration bits to Single Event-Multiple Upsets (SEMU). This thesis presents a Highly Available Fault-Tolerant Architecture (HAFTA) to protect SRAM-based FPGA designs against SEMUs in both configuration and user bits. In HAFTA, the entire design is duplicated and the main and replica flip-flops are compared at each clock cycle to detect any possible mismatch. To save the latest correct state of the... 

One of the most important characteristics of real-time systems is executing tasks before their specified deadlines. The tasks’ execution may require several resources like processor, I/O ports, and data structures. Some of these resources may be shared between several tasks and their availability is important in executing tasks before the deadlines. Allocating shared resources which are used in mutually exclusive manner often encounteres some problems such as priority inversion and deadlock. Resource access protocols are used to minimize or eliminate these problems. The effect of using these protocols issupporting tasks’ execution before their deadlines. To meet deadlines is of decisive...