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hoveida--mohaddeseh
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Mapping and Scheduling Applications onto Multi-Core Chip-Multiprocessors in Dark-Silicon Era
, M.Sc. Thesis Sharif University of Technology ; Sarbazi Azad, Hamid (Supervisor)
Abstract
Growing transistor counts, limited power budgets, and the breakdown of voltage scaling are currently conspiring to create a utilization wall that limits the fraction of a chip that can run at full speed at one time. This concept is the basis of the Dark Silicon definition. To address this issue, it is needed a structure to guaranty Limited power budget and obtain sufficient flexibility and performance for different applications with variety communication needs. Regarding to this structure, our aim is to present a platform for Networks-on-Chip that uses clustering and resource sharing among cores. Moreover, as task mapping on processing elements in NOCs is one of the most effective way to...
Ferritic-austenitic stainless steels dissimilar resistance spot welds: Metallurgical and failure characteristics
, Article Science and Technology of Welding and Joining ; Volume 21, Issue 6 , 2016 , Pages 438-445 ; 13621718 (ISSN) ; Khorramifar, M ; Hoveida Marashi, S. P ; Sharif University of Technology
Taylor and Francis Ltd
2016
Abstract
The paper addresses the microstructure and failure characteristics of dissimilar resistance spot welds between austenitic stainless steel and ferritic stainless steel. The fusion zone (FZ) of dissimilar welds exhibited complex microstructure consisting of ferrite, austenite and martensite. The development of this triplex structure in the FZ was explained by analysing the phase transformation path and austenite stability. Results showed that all dissimilar welds failed in partial thickness-partial pull-out failure mode. It was shown that the fraction of the nugget fracture of the weld is reduced by increasing the FZ size improving the mechanical performance of the weld. Peak load and energy...
Efficient mapping of applications for future chip-multiprocessors in dark silicon era
, Article ACM Transactions on Design Automation of Electronic Systems ; Volume 22, Issue 4 , 2017 ; 10844309 (ISSN) ; Aghaaliakbari, F ; Bashizade, R ; Arjomand, M ; Sarbazi Azad, H ; Sharif University of Technology
2017
Abstract
The failure of Dennard scaling has led to the utilization wall that is the source of dark silicon and limits the percentage of a chip that can actively switch within a given power budget. To address this issue, a structure is needed to guarantee the limited power budget along with providing sufficient flexibility and performance for different applications with various communication requirements. In this article, we present a generalpurpose platform for future many-core Chip-Multiprocessors (CMPs) that benefits from the advantages of clustering, Network-on-Chip (NoC) resource sharing among cores, and power gating the unused components of clusters. We also propose two task mapping methods for...
Revisiting processor allocation and application mapping in future CMPs in dark silicon era
, Article Advances in Computers ; Volume 110 , 2018 , Pages 35-81 ; 00652458 (ISSN); 9780128153581 (ISBN) ; Aghaaliakbari, F ; Jalili, M ; Bashizade, R ; Arjomand, M ; Sarbazi Azad, H ; Sharif University of Technology
Academic Press Inc
2018
Abstract
With technology advances and the emergence of new fabrication and VLSI technologies, current and future chip multiprocessors (CMPs) are expected to have tens to hundreds of processing elements and Gigabytes of on-chip caches, which are connected by a high bandwidth network-on-chip (NoC). Unfortunately, due to limited power budget of a computing system, specially for its processing element(s), it is impossible to keep all cores, caches, and network elements working at highest voltage level—that would resulted in dark silicon computing era, where by employing system-level or architecture-level techniques, one can keep a great portion of a CMP elements OFF (or in dim mode) to meet the power...
Effect of weld nugget size on overload failure mode of resistance spot welds
, Article Science and Technology of Welding and Joining ; Volume 12, Issue 3 , 2007 , Pages 217-225 ; 13621718 (ISSN) ; Asgari, H. R ; Mosavizadch, S. M ; Hoveida Marashi, P ; Goodarzi, M ; Sharif University of Technology
2007
Abstract
In the present paper, effects of welding current, welding time, electrode pressure and holding time on the weld nugget size were studied. A failure mechanism was proposed to describe both interfacial and pullout failure modes. This mechanism was confirmed by SEM investigations. In the light of this mechanism, the effect of welding parameters on static weld strength and failure mode was studied. Then, an analytical model was proposed to predict failure mode and to estimate minimum nugget diameter (critical diameter) to ensure pullout failure mode in shear tensile test. On the contrary to existing industrial standards, in this model, critical nugget diameter is attributed to metallurgical...
Peak load and energy absorption of DP600 advanced steel resistance spot welds
, Article Ironmaking and Steelmaking ; 2016 , Pages 1-8 ; 03019233 (ISSN) ; Pouranvari, M ; Salim, R. K ; Hashim, F. A ; Hoveida Marashi, S. P ; Sharif University of Technology
Taylor and Francis Ltd
2016
Abstract
The paper aims at investigating the microstructure, failure mode transition, peak load and energy absorption of DP600 dual phase steel during the tensile-shear test. It was found that the welding current has profound effect on the load–displacement characteristics. In the low welding current, welds failed in interfacial failure mode. Increasing welding current resulted in sufficient weld nugget growth to promote double-sided pullout failure mode with improved mechanical properties. Further increase in the welding current caused expulsion and failure mode was changed to single-sided pullout with reduced energy absorption capability. It was found that the fusion zone size is the key parameter...