Sharif Digital Repository

A routing algorithm defines a route which packet traverses to get to destination. In this research we study some kind of routing algorithms that are used in internal connections networks of multi-processor and multi-computers systems. Then we discuss about some routing algorithms which have been implemented network on chip architecture. First, we present a group of routing algorithms based on various criterions, and review so-called category. Afterwards, we study adaptive and deterministic routing algorithms and express circular model applying in internal connections networks and its governing rules in order to prevent dead lock. Then we survey adaptive algorithms such as Deflection routing,... 

Based on the observation that dynamic occurrence of zeros in the cache access stream and cache-resident memory values of ordinary programs exhibit a strong bias towards zero, this paper presents a novel CMOS five-transistor SRAM cell (5T SRAM cell) for very high density and low power cache applications. This cell retains its data with leakage current and positive feedback without refresh cycle. Novel 5T SRAM cell uses one word-line and one bit-line and extra read-line control. The new cell size is 17% smaller than a conventional six-transistor SRAM cell using same design rules with no performance degradation. Simulation and analytical results show purposed cell has correct operation during... 

The leakage current and process variation are drastically increased with technology scaling. In Conventional SRAM cell due to process variations, stored data can be destroyed during read operation. Therefore, leakage current of SRAM cell and stability during read operation are two important parameters in nano-scaled CMOS technology. To overcome these limitations and to increase the speed of conventional SRAMs, we have developed a read-static-noise-margin-free SRAM cell. The developed cell has six-transistors and uses two read/write-lines and two read/write-bit-lines during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The... 

In nano-scaled CMOS technology, the reduction of soft error rate and leakage current are the most important challenges in designing Field Programmable Gate Arrays (FPGA). To overcome these challenges, based on the observations that most configuration bit-streams of FPGA are zeros across different designs and that configuration memory cells are not directly involved with signal propagation delays in FPGA, this paper presents three new low-leakage and hardened configuration memory cells for nano-scaled CMOS technology. These cells are completely hardened when zeros are stored in the cells and cannot flip from particle strikes at the sensitive cell nodes. These cells retain their data with... 

As technology scales the area constraint is becoming less restrictive, but soft error rate and leakage current are drastically increased with technology down scaling. Therefore, in nano-scaled CMOS technology, the reduction of soft error rate and leakage current is the most important challenge in designing field programmable gate arrays (FPGA). To overcome these difficulties, based on the observations that most configuration bit-streams of FPGA are zeros across different designs and that configuration memory cells are not directly involved with signal propagation delays in FPGA, this paper presents a new family of configuration memory cells for FPGAs in nano-scaled CMOS technology. When... 

This paper proposes a low power SRAM based on five transistor SRAM cell. Proposed SRAM uses novel word-line decoding such that, during a read/write operation, only selected cell is connected to bit-line when one row is selected whereas, in conventional SRAM (CV-SRAM), all cells in selected row connected to their bit-lines, which in turn develops differential voltages across all bit-lines, and this makes energy consumption on unselected bit-lines. Proposed SRAM uses one bit-line and thus has lower bit-line leakage compared to CV-SRAM. Furthermore, the proposed SRAM incurs no area overhead, and has comparable read/write performance versus the CV-SRAM. Simulation results in standard 0.25μm CMOS... 

Based on the observation that dynamic occurrence of zeros in the cache access stream and cache-resident memory values of ordinary programs exhibit a strong bias towards zero, this paper presents a novel CMOS four-transistor (4T) SRAM cell for very high density and low power cache applications. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 20% smaller than a conventional six-transistor cell using same design rules and delay access of a cache based on new 4T SRAM cell is 32% smaller than a cache based on 6T SRAM cell. Also the dynamic and static power consumption of new cell is 40% and 20% smaller than 6T SRAM cell,... 

To help overcome limits to the density and speed of conventional SRAMs, we have developed a five-transistor SRAM cell. The newly developed CMOS five-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 18% smaller than a conventional six-transistor SRAM cell using same design rules. Simulation result in standard 0.25μm CMOS technology shows purposed cell has correct operation during read/write and idle mode. The average delay of new cell is 20% smaller than a six-transistor SRAM cell. © 2008 IEEE  

To help overcome limits to the density of conventional SRAMs and leakage current of SRAM cell in nanoscaled CMOS technology, we have developed a four-transistor SRAM cell. The newly developed CMOS four-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 19% smaller than a conventional six-transistor cell using same design rules. Also the leakage current of new cell is 60% smaller than a conventional sixtransistor SRAM cell. Simulation result in 65nm CMOS technology shows new cell has correct operation during read/write operation and idle mode  

As transistor dimensions are reduced due to technological advances, the area constraint is becoming less restrictive, but soft error rate, leakage current, and process variation are drastically increased. Therefore, in nano-scaled CMOS technology, soft error rate, leakage current and process variation are the most important issues in designing embedded cache memory. To overcome these challenges, and based on the observation that cache-resident memory values of ordinary programs exhibit a strong bias towards zero, this paper deals with new low leakage, hardened, and read-static-noise-margin-free SRAM memory cells for nano-scaled CMOS technology. These cells are completely hardened and cannot... 

In this study, an industrial acetylene hydrogenation unit is simulated utilizing three available kinetic models. The results are compared against six-day experimental data and the best model is selected. Effects of feed temperature and the amount of injected hydrogen on ethylene selectivity are also studied. According to the simulation results, the unit is not working under its optimum conditions. Furthermore, by reduction of the hydrogen flow rate to 52 kg/h, process selectivity is increased. In addition, a new approach is proposed to modify the hydrogenation process and reduce undesired by-products. In the simulation of the modified process, hydrogenation reactors temperature, hydrogen... 

In the present work, an unsymmetric laminated plate with surface bonded piezoelectric sensors, and actuators has been considered. Piezoelectric sensor were used to monitor the load and deformation bifurcation occurs. Monitoring the shape and load of a morphing structure is essential to ascertain that the structure is properly deployed and it is not loaded excessively, thus, preventing structural to failure. A piezoceramic actuator is used to provide activation load and to force the structure to change its stability state from one to another. A non-linear finite element model based on the layerwise displacement theory considering the electro-mechanical coupling effects of piezoelectric... 

Abstract In this study, Molecular Dynamics (MD) and Grand Canonical Monte Carlo (GCMC) simulations were conducted to investigate the diffusivity, solubility, and permeability of CO2, CO, H2, and H2O in a polyurethane membrane at three different temperatures. The characterization of the simulated structures was carried out using XRD, FFV, Tg and density calculation, and cavity size distribution. The obtained results were within the expectations reported data in the literature based on the experimental approach, indicating the authenticity of approached in this work. The results showed that the highest diffusivity and permeability coefficients were observed for... 

In this study, the effects of simultaneous co-deposition of polytetrafluoroethylene (PTFE) and MoS 2 particles on tribological properties of electroless nickel (EN) coating were studied. The influences of specimen orientation and heat treatment on EN-PTFE-MoS 2 composite coatings were also investigated. Scanning electron microscopy was used to study the morphology of coatings and the distributions of the lubricant particles in the deposits. Chemical analyses of coatings were done by electron dispersive spectrometry. The phases of the coatings were identified by X-ray diffraction utilizing CuKα radiation. Wear and friction properties of the coatings were also determined by pin-on-disk wear... 

In this paper, the design and measurement of a high gain active calibration target (ACT) for millimeter wave imaging system is presented. Increasing the radar cross section in ACT improves the calibration accuracy. For this purpose, we designed a high-gain array antenna, which consists of 32 planar patch elements. The measured antenna bandwidth is 3.5 GHz (26.5-30 GHz) and the peak realized gain is over 19.5 dBi. In addition, in the ACT design, switching between 4 loads instead of 2 loads is proposed to increase the precision of calibration. The measured results confirm the validity of the designed ACT circuit. The implemented ACT can be used for fast in-situ calibration of millimeter wave... 

A large number of generators failed due to stator winding problems, mainly insulation deterioration. Insulation degradation assessment plays vital role in the asset life management. Electro thermal analysis is the main characteristic for simulation of generator behavior and to improve the design of stator slot's insulation. Dielectric parameters such as insulation thickness, spacing, material types, geometry of winding and slot are major design consideration. A very powerful method available to analyze electro thermal performance is Finite Element Method (FEM) which is used in this paper. The analysis of various stator coil and slot configurations are used to design the better dielectric... 

Properties of FeCo nanocrystalline intermetallic powders prepared by salt-matrix hydrogen reduction of a milled Fe 2O 3-Co 3O 4 mixture were investigated. The product of 72 ks ball-milling at 350 rpm was CoFe 2O 4 nanopowder. Reduction of this powder for 3.6 ks by hydrogen at 750 °C resulted in the formation of Fe 0.67Co 0.33 stoichiometric compound. Scanning electron microscopy, electron dispersive spectrometry, X-ray diffraction and vibrating sample magnetometry were used to characterize the nanopowder. Using a salt-matrix (NaCl as a dispersion medium) resulted in the decrease of the reduction temperature and improvement of the morphology and magnetic properties of the nanopowder.... 

In this paper, the problem of formation control with regard to leader–follower mobile robots in the presence of disturbances and model uncertainties, without needing to know the velocity of the leader robot, is presented. For this purpose, at first, a first-order kinematic model of leader–follower and leader–leader formations is obtained, and considering the absolute velocity of the leader robots as an uncertainty, a robust adaptive controller is designed to keep the desired formation. In this case, the upper bound of uncertainty is unknown and is obtained via stable adaptive laws. Afterwards, in order to deal with the accelerated robots and obstacles, second-order leader–follower and... 

The compaction forming of metal powder is a process involving large deformations, large strain, non-linear material behavior and friction. Consequently, the numerical analysis of such a highly non-linear process is a formidable computational problem. In this paper, an ALE technique is presented based on a generalized cap plasticity model in simulation of powder forming processes. In ALE formulation, the reference configuration is used for describing the motion, instead of material configuration in Lagrangian, and spatial configuration in Eulerian formulation. This formulation introduces some convective terms in the finite element equations and consists of two phases. Each time step is... 

Observability of bulk power transmission network by means of minimum number of phasor measurement units (PMUs), with the aid of the network topology, is a great challenge. This paper presents a novel equivalent integer linear programming method (EILPM) for the exhaustive search-based PMU placement. The state estimation implemented based on such a placement is completely linear, thereby eliminating drawbacks of the conventional SCADA-based state estimation. Additional constraints for observability preservation following single PMU or line outages can easily be implemented in the proposed EILPM. Furthermore, the limitation of communication channels is dealt with by translation of nonlinear...